REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Optimal VLSI architectural synthesis: area, performance and testability
Optimal VLSI architectural synthesis: area, performance and testability
Adaptive filter theory (2nd ed.)
Adaptive filter theory (2nd ed.)
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
HYPER-LP: a system for power minimization using architectural transformations
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Principles of Digital Communication and Coding
Principles of Digital Communication and Coding
Information Theory and Reliable Communication
Information Theory and Reliable Communication
Behavioral Synthesis for low Power
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
A new parameterizable power macro-model for datapath components
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Lower and upper bounds on the switching activity in scheduled data flow graphs
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Conditional speculation and its effects on performance and area for high-level snthesis
Proceedings of the 14th international symposium on Systems synthesis
Lower bound estimation for low power high-level synthesis
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Bus optimization for low-power data path synthesis based on network flow method
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An integrated data path optimization for low power based on network flow method
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Power Macro-Modelling for Firm-Macro
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Coupling-aware high-level interconnect synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Game-Theoretic Approach for Binding in Behavioral Synthesis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
High-level synthesis for low power based on network flow method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
A low power scheduler using game theory
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Dynamic Functional Unit Assignment for Low Power
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Temperature-aware resource allocation and binding in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
Dynamic functional unit assignment for low power
The Journal of Supercomputing
Optimal module and voltage assignment for low-power
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Effective techniques for the generalized low-power binding problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimal simultaneous module and multivoltage assignment for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimality study of resource binding with multi-Vdds
Proceedings of the 43rd annual Design Automation Conference
Reducing power while increasing performance with supercisc
ACM Transactions on Embedded Computing Systems (TECS)
Thermal-induced leakage power optimization by redundant resource allocation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
REWIRED: REgister Write Inhibition by REsource Dedication
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Pipelining with common operands for power-efficient linear systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A game theoretic approach for power optimization during behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal-aware datapath merging for coarse-grained reconfigurable processors
Proceedings of the Conference on Design, Automation and Test in Europe
HLS-dv: a high-level synthesis framework for dual-Vdd architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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