IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Module assignment for low power
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Scheduling techniques for variable voltage low power designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Datapath scheduling with multiple supply voltages and level converters
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Maximum current estimation considering power gating
Proceedings of the 2001 international symposium on Physical design
A low power scheduling scheme with resources operating at multiple voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Evaluating Run-Time Techniques for Leakage Power Reduction
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Low-power high-level synthesis for FPGA architectures
Proceedings of the 2003 international symposium on Low power electronics and design
High-level synthesis for low power based on network flow method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Low-power technology mapping for FPGA architectures with dual supply voltages
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
FPGA power reduction using configurable dual-Vdd
Proceedings of the 41st annual Design Automation Conference
Register binding and port assignment for multiplexer optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Optimality study of resource binding with multi-Vdds
Proceedings of the 43rd annual Design Automation Conference
Simultaneous FU and register binding based on network flow method
Proceedings of the conference on Design, automation and test in Europe
Variation-aware layout-driven scheduling for performance yield optimization
Proceedings of the International Conference on Computer-Aided Design
HLS-dv: a high-level synthesis framework for dual-Vdd architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Combining module selection and replication for throughput-driven streaming programs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Combining computation and communication optimizations in system synthesis for streaming applications
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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Reducing power consumption through high-level synthesis has attracted a growing interest from researchers due to its large potential for power reduction. In this work we study functional unit binding (or module assignment) given a scheduled data flow graph under a dual-Vdd framework. We assume that each functional unit can be driven by a low Vdd or a high Vdd dynamically during run time to save dynamic power. We develop a polynomial-time optimal algorithm for assigning low Vdd to as many operations as possible under the resource and time constraint, and in the same time minimizing total switching activity through functional unit binding. Our algorithm shows consistent improvement over a design flow that separates voltage assignment from functional unit binding. We also change the initial scheduling to examine power-latency tradeoff scenarios. Experimental results show that we can achieve a 21% power reduction when latency bound is tight. When latency is relaxed by 10 to 100%, the power reduction is 31 to 73% compared to the synthesis results for the case of single high Vdd without latency relaxation. We also show comparison data of energy consumption under the same experimental setting.