REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Simultaneous scheduling and binding for power minimization during microarchitecture synthesis
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Module assignment for low power
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Scheduling techniques for variable voltage low power designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Datapath scheduling with multiple supply voltages and level converters
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low energy memory and register allocation using network flow
DAC '97 Proceedings of the 34th annual Design Automation Conference
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Layout techniques supporting the use of dual supply voltages for cell-based designs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
New methods to color the vertices of a graph
Communications of the ACM
High-level synthesis under multi-cycle interconnect delay
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A low power scheduling scheme with resources operating at multiple voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Bus optimization for low-power data path synthesis based on network flow method
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Pushing ASIC performance in a power envelope
Proceedings of the 40th annual Design Automation Conference
Resource Allocation and Binding Approach for Low Leakage Power
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Register binding and port assignment for multiplexer optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Leakage power optimization with dual-Vth library in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
Optimal module and voltage assignment for low-power
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Rapid estimation of control delay from high-level specifications
Proceedings of the 43rd annual Design Automation Conference
Optimality study of resource binding with multi-Vdds
Proceedings of the 43rd annual Design Automation Conference
Register allocation for high-level synthesis using dual supply voltages
Proceedings of the 46th Annual Design Automation Conference
Scheduling with multiple voltages
Integration, the VLSI Journal
Leakage power analysis and reduction during behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On effective slack management in postscheduling phase
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Dual supply voltage design is widely accepted as an effective way to reduce the power consumption of CMOS circuits. In this paper, we propose a comprehensive design framework that includes dual-Vdd scheduling, dual- Vdd allocation, controller synthesis as well as layout generation. In particular, we address a problem of high-level synthesis with objective of minimizing power consumption of storage units and multiplexers using dual- Vdd; this is made possible by utilizing timing slack that is left in the data-path after operation scheduling. We use integer linear programming (ILP) and also provide heuristic algorithms to solve the dual- Vdd register and connection allocation. The physical layout of dual- Vdd circuits has to separate power rails of Vddh and Vddl cells from each other. We propose a voltage island based placement algorithm to relieve this restriction and allow more flexibility of placement. In experiments on benchmark designs implemented in 1.08 V (with Vddl of 0.8 V) 65-nm CMOS technology, both switching and leakage power are reduced by 20% on average, respectively, compared to data-path with dual- Vdd applied to functional units alone. Detailed analysis of area and wirelength is performed to assess feasibility of the proposed method.