Low-power operation using self-timed circuits and adaptive scaling of the supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Precomputation-based sequential logic optimization for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A survey of optimization techniques targeting low power VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Simultaneous scheduling and binding for power minimization during microarchitecture synthesis
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
High-level synthesis techniques for reducing the activity of functional units
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Retiming sequential circuits for low power
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
SYCLOP: Synthesis of CMOS Logic for Low Power Applications
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Behavioral Synthesis for low Power
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Microarchitectural Synthesis of Performance-Constrained, Low-Power VLSI Designs
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
On multiple-voltage high-level synthesis using algorithmic transformations
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Temperature aware datapath scheduling
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Low-energy-transmission of data on submicron interconnects
WSEAS TRANSACTIONS on COMMUNICATIONS
HLS-dv: a high-level synthesis framework for dual-Vdd architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a low power design technique at the behavioral synthesis stage. A scheduling technique for low power is studied and a theoretical foundation is established. The equation for dynamic power, P"d"y"n = V"d"d^2"l"o"a"df"s"w"i"t"c"h, is used as a basis. The voltage applied to the functional units is varied, slowing down the functional unit throughput and reducing the power while meeting the throughput constraint for the entire system. The input to our problem is an unscheduled data flow graph with a timing constraint. The goal is to establish a voltage value at which each of the operations of the data flow graph would be performed, thereby fixing the latency for the operation such that the total timing constraint for the system is met. We give an algorithm to minimize the system's power; the algorithm finds an optimal schedule. The timing constraint for our system could be any value greater than or equal to the critical path. The experimental results for some high-level synthesis benchmarks show considerable reduction in the power consumption. Using 5 and 3 V supply voltages we achieve a maximum reduction of approximately 40% given tight timing constraints. Similarly, we obtain a 46% reduction using 5, 3 and 2.4V supply voltages. For larger timing constraints, the maximum reduction is about 64% using 5 and 3 V supply voltages and a maximum reduction of about 74% using 5, 3 and 2.4 V supply voltages.