Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Design considerations and tools for low-voltage digital system design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Scheduling techniques for variable voltage low power designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Datapath scheduling with multiple supply voltages and level converters
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low power scheduling scheme with resources operating at multiple voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Proceedings of the 2003 international symposium on Low power electronics and design
Proceedings of the 2004 international symposium on Low power electronics and design
Scheduling with multiple voltages
Integration, the VLSI Journal
| Hi-index | 0.00 |
This paper presents temperature aware low power scheduling under resource and latency constraints. We assume resources with different energy delay values are available. These resources are optimized in terms of energy for a certain delay, using variable supply voltage, multiple threshold voltages and sizing techniques. The proposed algorithms are based on temperature and power efficient distribution of slack among the nodes in the data-flow graph. The distribution procedure tries to implement the minimum energy scheduling when there is no temperature critical points. If a functional unit reaches a critical temperature, algorithm tries not to schedule any nodes in the data flow graph to high temperature resources, thus decrease the chip temperature. Experiments with some HLS benchmark examples show that the proposed algorithms achieve significant power/energy reduction. For instance, when the latency constraint is 2 times the critical path delay and one of the resource temperature is critical the average power reduction is 50.8% and utilization of the hot resource is average 1%.