Proceedings of the 39th annual Design Automation Conference
Sub-90nm technologies: challenges and opportunities for CAD
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2003 international symposium on Low power electronics and design
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation
Proceedings of the 2004 international symposium on Low power electronics and design
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Proceedings of the 42nd annual Design Automation Conference
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Technology mapping for low leakage power and high speed with hot-carrier effect consideration
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Achieving continuous VT performance in a dual VT process
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization
Proceedings of the 2006 international symposium on Physical design
An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 2007 international symposium on Physical design
Digital Circuit Optimization via Geometric Programming
Operations Research
Device-aware yield-centric dual-Vt design under parameter variations in nanoscale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Implementation of low power adder design and analysis based on power reduction technique
Microelectronics Journal
The epsilon-approximation to discrete VT assignment for leakage power minimization
Proceedings of the 2009 International Conference on Computer-Aided Design
Post-manufacture tuning for nano-CMOS yield recovery using reconfigurable logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual-Vt assignment policies in ITD-aware synthesis
Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Post sign-off leakage power optimization
Proceedings of the 48th Design Automation Conference
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part I
Application of very fast simulated reannealing (VFSR) to low power design
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Temperature aware datapath scheduling
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Construction of realistic gate sizing benchmarks with known optimal solutions
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
Post-synthesis leakage power minimization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digital random logic complementary metal-oxide-semiconductor (CMOS) circuit for a dual-threshold voltage process. The tradeoff between static and dynamic power consumption has been explored. When used along with device sizing and supply voltage reduction techniques for low power, the proposed algorithm can reduce the total power dissipation of a circuit by as much as 50%.