Discrete Vt assignment and gate sizing using a self-snapping continuous formulation

Authors:
S. Shah;A. Srivastava;D. Sharma;D. Sylvester;D. Blaauw;V. Zolotov
Affiliations:
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA;Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA;Dept. of Electr. Eng., California Univ., Riverside, CA, USA;Berkeley Design Autom., Santa Clara, CA, USA;Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA;-
Venue:
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Year:
2005

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Abstract

This paper presents a novel approach towards the simultaneous Vt-assignment and gate-sizing problem. This inherently discrete problem is formulated as a continuous problem, allowing it to be solved using any of several widely available and highly efficient non-linear optimizers. We prove that, under our formulation, the optimal solution has discrete Vts assigned to almost every gate, thus eliminating the need for a sophisticated snapping heuristic. We show that this technique performs dual-Vt assignment and gate sizing in a very efficient manner. Compared to a sensitivity based method, we achieve average leakage savings of 31% and average total power savings of 7.4% with very efficient runtimes.