Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Analog VLSI signal processing: why, where, and how?
Journal of VLSI Signal Processing Systems - Joint special issue on Analog VLSI computation; also see Analog Integrated Circuits Signal Process., Vol. 6, No. 1
Transistor reordering for low power CMOS gates using an SP-BDD representation
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Device-circuit optimization for minimal energy and power consumption in CMOS random logic networks
DAC '97 Proceedings of the 34th annual Design Automation Conference
Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design and optimization of low voltage high performance dual threshold CMOS circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Static power optimization of deep submicron CMOS circuits for dual VT technology
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Mixed-Vth (MVT) CMOS circuit design methodology for low power applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Leakage control with efficient use of transistor stacks in single threshold CMOS
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Methods for true power minimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Static leakage reduction through simultaneous threshold voltage and state assignment
Proceedings of the 40th annual Design Automation Conference
Leakage and leakage sensitivity computation for combinational circuits
Proceedings of the 2003 international symposium on Low power electronics and design
Active leakage power optimization for FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization
Proceedings of the conference on Design, automation and test in Europe - Volume 1
LECTOR: a technique for leakage reduction in CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Selective gate-length biasing for cost-effective runtime leakage control
Proceedings of the 41st annual Design Automation Conference
Tradeoffs between date oxide leakage and delay for dual Tox circuits
Proceedings of the 41st annual Design Automation Conference
Analytical models for leakage power estimation of memory array structures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Defocus-aware leakage estimation and control
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Statistical technology mapping for parametric yield
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An analytical state dependent leakage power model for FPGAs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Standard cell library optimization for leakage reduction
Proceedings of the 43rd annual Design Automation Conference
A statistical framework for post-silicon tuning through body bias clustering
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Digital Circuit Optimization via Geometric Programming
Operations Research
Leakage power reduction using stress-enhanced layouts
Proceedings of the 45th annual Design Automation Conference
A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Mechanical stress aware optimization for leakage power reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Eyecharts: constructive benchmarking of gate sizing heuristics
Proceedings of the 47th Design Automation Conference
Recovery-driven design: a power minimization methodology for error-tolerant processor modules
Proceedings of the 47th Design Automation Conference
Dual-Vt assignment policies in ITD-aware synthesis
Microelectronics Journal
Slack redistribution for graceful degradation under voltage overscaling
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gate oxide leakage and delay tradeoffs for dual-toxcircuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Runtime leakage minimization through probability-aware optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Construction of realistic gate sizing benchmarks with known optimal solutions
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Discrete sizing for leakage power optimization in physical design: A comparative study
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Post-synthesis leakage power minimization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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We present a new approach for the estimation and optimization of standby power dissipation in large MOS digital circuits. We first introduce a new approach for accurate and efficient calculation of the average standby or leakage current in large digital circuits by introducing the concepts of "dominant leakage states" and the use of state probabilities. Combined with graph reduction techniques and simplified nonlinear simulation, our method achieves speedups of three to four orders of magnitude over exhaustive SPICE simulations while maintaining very good accuracy. The leakage current calculation is then utilized in a new leakage and performance optimization algorithm for circuits using dual Vt processes. Our approach is the first to consider the assignment of both the Vt and the width of a transitor, simultaneously. Our optimization approach was able to obtain 81-100% of the performance achievable with all low Vt transistors, but with 1/3 to 1/6 the standby current. We also show that knowledge of the standby state of the device enhances the leakage/performance tradeoff.