A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Topological Analysis for Leakage Prediction of Digital Circuits
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Probabilistic modeling of dependencies during switching activity analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient techniques for gate leakage estimation
Proceedings of the 2003 international symposium on Low power electronics and design
Execution cache-based microarchitecture power-efficient superscalar processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variability and energy awareness: a microarchitecture-level perspective
Proceedings of the 42nd annual Design Automation Conference
Toward a multiple clock/voltage island design style for power-aware processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Prediction of leakage power under process uncertainties
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Statistical leakage estimation based on sequential addition of cell leakage currents
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Customizing pattern set for test power reduction via improved X-identification and reordering
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Integration, the VLSI Journal
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Power Modeling and Characterization of Computing Devices: A Survey
Foundations and Trends in Electronic Design Automation
Efficient statistical leakage analysis using deterministic cell leakage models
Microelectronics Journal
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Leakage power is emerging as a new critical challenge in the design of high performance integrated circuits. Leakage is increasing dramatically with each technology generation and is expected to dominate system power. This paper describes a static (i.e input independent) technique for efficient and accurate leakage estimation. A probabilistic technique is presented to compute the average leakage of combinational circuits. The proposed technique gives accurate results with an average error of only 2% for the ISCAS benchmarks and accurately predict both subthreshold and gate leakage as well as the leakage sensitivities to process and environmental parameters.