Efficient techniques for gate leakage estimation

Authors:
Rahul M. Rao;Jeffrey L. Burns;Anirudh Devgan;Richard B. Brown
Affiliations:
University of Michigan, Ann Arbor, MI;IBM, Austin, TX;IBM, Austin, TX;University of Michigan, Ann Arbor, MI
Venue:
Proceedings of the 2003 international symposium on Low power electronics and design
Year:
2003

Citing 2
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Abstract

Gate leakage current is expected to be the dominant leakage component in future technology generations. In this paper, we propose methods for steady-state gate leakage estimation based on state characterization. An efficient technique for pattern-dependent gate leakage estimation is presented. Further, we propose the use of this technique for estimating the average gate leakage of a circuit using pattern-independent probabilistic analysis. Results on a large set of benchmark ISCAS circuits show an accuracy within 5% of SPICE results with 500X to 50000X speed improvement.