Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms

Authors:
Paulo F. Butzen;Leomar S. Rosa Jr.;Erasmo J.D. Chiappetta Filho;Dionatan S. Moura;Andre I. Reis;Renato P. Ribas
Affiliations:
UFRGS, Porto Alegre, Brazil;UFRGS, Porto Alegre, Brazil;UFRGS, Porto Alegre, Brazil;UFRGS, Porto Alegre, Brazil;Nangate, Menlo Park, CA, USA;UFRGS, Porto Alegre, Brazil
Venue:
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Year:
2008

Citing 9
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Abstract

This paper proposes a new method to estimate static power dissipation in digital circuits by evaluating simultaneously subthreshold and gate oxide leakage currents. The estimation method is performed over logic cells, including CMOS complex gates with multi-level series-parallel devices. Experimental results have been carried out on different fabrications processes, and good correlation with HSPICE simulator was obtained at cell and circuit levels. The algorithm presents a speed up of 80x when compared to HSPICE.