Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions
Proceedings of the 43rd annual Design Automation Conference
Statistical analysis of full-chip leakage power considering junction tunneling leakage
Proceedings of the 44th annual Design Automation Conference
Statistical performance modeling and optimization
Foundations and Trends in Electronic Design Automation
Full-chip leakage current estimation based on statistical sampling techniques
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
A probabilistic technique for full-chip leakage estimation
Proceedings of the 13th international symposium on Low power electronics and design
Layout-dependent STI stress analysis and stress-aware RF/analog circuit design optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
Rapid design space exploration using legacy design data and technology scaling trend
Integration, the VLSI Journal
Full-chip leakage analysis for 65nm CMOS technology and beyond
Integration, the VLSI Journal
Scaling of analog LDPC decoders in sub-100nm CMOS processes
Integration, the VLSI Journal
Low-power subthreshold to above threshold level shifters in 90nm and 65nm process
Microprocessors & Microsystems
Accuracy analysis of power characterization and modeling
ICHIT'11 Proceedings of the 5th international conference on Convergence and hybrid information technology
First integration of MOSFET band-to-band-tunneling current in BSIM4
Microelectronics Journal
Testing methodology of embedded DRAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Dramatic increase of subthreshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage in scaled devices results in the drastic increase of total leakage power in a logic circuit. In this paper, a methodology for accurate estimation of the total leakage in a logic circuit based on the compact modeling of the different leakage current in nanoscaled bulk CMOS devices has been developed. Current models have been developed based on the device geometry, two-dimensional doping profile, and operating temperature. A circuit-level model of junction BTBT leakage has been developed. Simple models of the subthreshold current and the gate current have been presented. Also, the impact of quantum mechanical behavior of substrate electrons, on the circuit leakage has been analyzed. Using the compact current model, a transistor has been modeled as a sum of current sources (SCS). The SCS transistor model has been used to estimate the total leakage in simple logic gates and complex logic circuits (designed with transistors of 25-nm effective length) at room and elevated temperatures.