The design and use of simplepower: a cycle-accurate energy estimation tool
Proceedings of the 37th Annual Design Automation Conference
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Slope propagation in static timing analysis
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Itanium 2 Processor Microarchitecture
IEEE Micro
T3: Trends and Challenges in VLSI Technology Scaling towards 100nm
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Toward Design Technology in 2020: Trends, Issues, and Challenges
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Impact of Technology Scaling in the Clock System Power
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Design technology challenges for system and chip level designs in very deep submicron technologies
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies
Proceedings of the 2004 international symposium on Low power electronics and design
IBM Journal of Research and Development
Power Switch Network Design for MTCMOS
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Challenges in sleep transistor design and implementation in low-power designs
Proceedings of the 43rd annual Design Automation Conference
Low power design from technology challenge to great products
Proceedings of the 2006 international symposium on Low power electronics and design
Power andPerformance Analysis for Early Design Space Exploration
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Fast and Accurate Waveform Analysis with Current Source Models
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
A fast and elitist multiobjective genetic algorithm: NSGA-II
IEEE Transactions on Evolutionary Computation
IEEE Transactions on Evolutionary Computation
Platune: a tuning framework for system-on-a-chip platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Rapid and effective design space exploration at all stages of a design process enables faster design convergence and shorter time-to-market. This is particularly important during the early stage of a design where design decisions can have a significant impact on design convergence. This paper describes a methodology for design space exploration using design target prediction models. These models are driven by legacy design data, technology scaling trends and, an in situ model-fitting process. Experiments on ISCAS benchmark circuits validate the feasibility of the proposed approach and yielded power centric designs that improved power by 7-32% for a corresponding 0-9% performance impact; or performance centric designs with improved performance of 10.31-17% for a corresponding 2-3.85% power penalty. Evolutionary algorithm based Pareto analysis on an industrial 65nm design uncovered design tradeoffs which are not obvious to designers and optimize both power and performance. The high performance design option of the industrial design improved the straight-ported design's performance by 29% with a 2.5% power penalty, whereas the low power design option reduced the straight-ported design's power consumption by 40% for a 9% performance penalty.