Digital Technical Journal - Special 10th anniversary issue
Power considerations in the design of the Alpha 21264 microprocessor
DAC '98 Proceedings of the 35th annual Design Automation Conference
Energy optimization of multilevel cache architectures for RISC and CISC processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Energy-driven integrated hardware-software optimizations using SimplePower
Proceedings of the 27th annual international symposium on Computer architecture
Testing for Function and Performance: Towards anIntegrated Processor Validation Methodology
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
The optimum pipeline depth for a microprocessor
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Increasing processor performance by implementing deeper pipelines
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Proceedings of the 2002 international symposium on Low power electronics and design
Design Challenges of Technology Scaling
IEEE Micro
Optimizing pipelines for power and performance
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A technique to determine power-efficient, high-performance superscalar processors
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
Design and modeling of power-efficient computer architectures
Design and modeling of power-efficient computer architectures
Balancing hardware intensity in microprocessor pipelines
IBM Journal of Research and Development
POWER3: the next generation of PowerPC processors
IBM Journal of Research and Development
POWER4 system microarchitecture
IBM Journal of Research and Development
Understanding the energy efficiency of simultaneous multithreading
Proceedings of the 2004 international symposium on Low power electronics and design
Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
The need for a full-chip and package thermal model for thermally optimized IC designs
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A performance-conserving approach for reducing peak power consumption in server systems
Proceedings of the 19th annual international conference on Supercomputing
Simulation of Computer Architectures: Simulators, Benchmarks, Methodologies, and Recommendations
IEEE Transactions on Computers
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
POWER5 System microarchitecture
IBM Journal of Research and Development - POWER5 and packaging
Accurate and efficient regression modeling for microarchitectural performance and power prediction
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Impact of process variations on multicore performance symmetry
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 22nd ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware
EURASIP Journal on Applied Signal Processing
Performance modeling for early analysis of multi-core systems
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Efficiency trends and limits from comprehensive microarchitectural adaptivity
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
Exploring power management in multi-core systems
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Instruction-driven clock scheduling with glitch mitigation
Proceedings of the 13th international symposium on Low power electronics and design
Power-Aware Design via Micro-architectural Link to Implementation
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Toward a multicore architecture for real-time ray-tracing
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 46th Annual Design Automation Conference
Research on synthesis parameter real-time scheduling algorithm on multi-core architecture
CCDC'09 Proceedings of the 21st annual international conference on Chinese control and decision conference
Rapid design space exploration using legacy design data and technology scaling trend
Integration, the VLSI Journal
Power-efficient, reliable microprocessor architectures: modeling and design methods
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis
Proceedings of the 37th annual international symposium on Computer architecture
Proceedings of the 47th Design Automation Conference
Applied inference: Case studies in microarchitectural design
ACM Transactions on Architecture and Code Optimization (TACO)
Power and performance aware reconfigurable cache for CMPs
Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy consumption and execution time estimation of embedded system applications
Microprocessors & Microsystems
Proceedings of the 48th Design Automation Conference
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
ACM Transactions on Architecture and Code Optimization (TACO)
A survey on cache tuning from a power/energy perspective
ACM Computing Surveys (CSUR)
Performance analysis of multi-threaded multi-core CPUs
Proceedings of the First International Workshop on Many-core Embedded Systems
Formal verification of architectural power intent
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power management of multi-core chips: challenges and pitfalls
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The PowerTimer toolset has been developed for use in early-stage, microarchitecture-level power-performance analysis of microprocessors. The key component of the toolset is a parameterized set of energy functions that can be used in conjunction with any given cycle-accurate microarchitectural simulator. The energy functions model the power consumption of primitive and hierarchically composed building blocks which are used in microarchitecture-level performance models. Examples of structures modeled are pipeline stage latches, queues, buffers and component read/write multiplexers, local clock buffers, register files, and cache array macros. The energy functions can be derived using purely analytical equations that are driven by organizational, circuit, and technology parameters or behavioral equations that are derived from empirical, circuit-level simulation experiments. After describing the modeling methodology, we present analysis results in the context of a current-generation superscalar processor simulator to illustrate the use and effectiveness of such early-stage models. In addition to average power and performance tradeoff analysis, PowerTimer is useful in assessing the typical and worst-case power (or current) swings that occur between successive cycle windows in a given workload execution. Such a characterization of workloads at the early stage of microarchitecture definition helps pinpoint potential inductive noise problems on the voltage rail that can be addressed by designing an appropriate package or by suitably tuning the dynamic power management controls within the processor.