Gradient-based optimization of custom circuits using a static-timing formulation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Optimization of high-performance superscalar architectures for energy efficiency
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Low-power CMOS with supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clocking strategies and scannable latches for low power appliacations
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Unified architecture level energy-efficiency metric
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Energy-delay efficiency of VLSI computations
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Energy efficient CMOS microprocessor design
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
Methods for true power minimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Optimizing pipelines for power and performance
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
RTAS '03 Proceedings of the The 9th IEEE Real-Time and Embedded Technology and Applications Symposium
Optimum Power/Performance Pipeline Depth
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Optimization of scannable latches for low energy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Design methodology for semi custom processor cores
Proceedings of the 14th ACM Great Lakes symposium on VLSI
An innovative low-power high-performance programmable signal processor for digital communications
IBM Journal of Research and Development
Balancing hardware intensity in microprocessor pipelines
IBM Journal of Research and Development
IBM Journal of Research and Development
Clocking and clocked storage elements in a multi-gigahertz environment
IBM Journal of Research and Development
High performance level conversion for dual VDD design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The optimum pipeline depth considering both power and performance
ACM Transactions on Architecture and Code Optimization (TACO)
On the energy-efficiency of speculative hardware
Proceedings of the 2nd conference on Computing frontiers
Architectural Considerations for Energy Efficiency
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Towards formal probabilistic power-performance design space exploration
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Energy optimization of pipelined digital systems using circuit sizing and supply scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Investigating cache energy and latency break-even points in high performance processors
MEDEA '06 Proceedings of the 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures
Evaluating trace cache energy efficiency
ACM Transactions on Architecture and Code Optimization (TACO)
Investigating cache energy and latency break-even points in high performance processors
ACM SIGARCH Computer Architecture News
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
The mixed signal optimum energy point: voltage and parallelism
Proceedings of the 45th annual Design Automation Conference
Leakage power reduction using stress-enhanced layouts
Proceedings of the 45th annual Design Automation Conference
STEEL: a technique for stress-enhanced standard cell library design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Dynamic MIPS rate stabilization in out-of-order processors
Proceedings of the 36th annual international symposium on Computer architecture
Area-efficiency in CMP core design: co-optimization of microarchitecture and physical design
ACM SIGARCH Computer Architecture News
Power scalability in a mesh-connected reconfigurable architecture
ACM Transactions on Embedded Computing Systems (TECS)
Power-efficient, reliable microprocessor architectures: modeling and design methods
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis
Proceedings of the 37th annual international symposium on Computer architecture
Mechanical stress aware optimization for leakage power reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Stacking SRAM banks for ultra low power standby mode operation
Proceedings of the 47th Design Automation Conference
HERQULES: system level cross-layer design exploration for efficient energy-quality trade-offs
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
General strategies to design nanometer flip-flops in the energy-delay space
IEEE Transactions on Circuits and Systems Part I: Regular Papers
An integrated framework for joint design space exploration of microarchitecture and circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Finding the energy efficient curve: gate sizing for minimum power under delay constraints
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
From energy-delay metrics to constraints on the design of digital circuits
International Journal of Circuit Theory and Applications
Performance analysis of multi-threaded multi-core CPUs
Proceedings of the First International Workshop on Many-core Embedded Systems
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Evaluation of architectural tradeoffs is complicated by implications in the circuit domain which are typically not captured in the analysis but substantially affect the results. We propose a metric of hardware intensity (&eegr;), which is useful for evaluating issues that affect both circuits and architecture. Analyzing data for actual designs we show how to measure the introduced parameters and discuss variations between observed results and common theoretical assumptions. For a power-efficient design we derive relations for &eegr; and supply voltage V under progressively more general situations, and incorporate &eegr; into a prior art architectural energy-efficiency criterion. Then, a more general relation is derived for the optimal balance between the architectural complexity, hardware intensity and power supply. Modified forms for these relations are obtained in special cases where the supply voltage is constrained or when clock gating is disallowed.