Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis

  • Authors:

  • Omid Azizi;Aqeel Mahesri;Benjamin C. Lee;Sanjay J. Patel;Mark Horowitz

  • Affiliations:

  • Stanford University, Stanford, CA, USA;NVIDIA Corporation, Santa Clara, CA, USA;Stanford University, Stanford, CA, USA;University of Illinois at Urbana-Champaign, Urbana, IL, USA;Stanford University, Stanford, CA, USA

  • Venue:
  • Proceedings of the 37th annual international symposium on Computer architecture
  • Year:
  • 2010

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Abstract

Power consumption has become a major constraint in the design of processors today. To optimize a processor for energy-efficiency requires an examination of energy-performance trade-offs in all aspects of the processor design space, including both architectural and circuit design choices. In this paper, we apply an integrated architecture-circuit optimization framework to map out energy-performance trade-offs of several different high-level processor architectures. We show how the joint architecture-circuit space provides a trade-off range of approximately 6.5x in performance for 4x energy, and we identify the optimal architectures for different design objectives. We then show that many of the designs in this space come at very high marginal costs. Our results show that, for a large range of design objectives, voltage scaling is effective in efficiently trading off performance and energy, and that the choice of optimal architecture and circuits does not change much during voltage scaling. Finally, we show that with only two designs--a dual-issue in-order design and a dual-issue out-of-order design, both properly optimized-a large part of the energy-performance trade-off space can be covered within 3% of the optimal energy-efficiency.