Efficiency trends and limits from comprehensive microarchitectural adaptivity
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ACM Transactions on Computer Systems (TOCS)
Modeling program resource demand using inherent program characteristics
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ACM SIGMETRICS Performance Evaluation Review
ACM Transactions on Embedded Computing Systems (TECS)
Microarchitectural design space exploration made fast
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HaDeS: architectural synthesis for heterogeneous dark silicon chip multi-processors
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Wimpy or brawny cores: A throughput perspective
Journal of Parallel and Distributed Computing
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ACM Transactions on Computer Systems (TOCS)
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We apply a scalable approach for practical, comprehensive design space evaluation and optimization. This approach combines design space sampling and statistical inference to identify trends from a sparse simulation of the space. The computational efficiency of sampling and inference enables new capabilities in design space exploration. We illustrate these capabilities using performance and power models for three studies of a 260,000 point design space: (1) pareto frontier analysis, (2) pipeline depth analysis, and (3) multiprocessor heterogeneity analysis. For each study, we provide an assessment of predictive error and sensitivity of observed trends to such error. We construct pareto frontiers and find predictions for pareto optima are no less accurate than those for the broader design space. We reproduce and enhance prior pipeline depth studies, demonstrating constrained sensitivity studies may not generalize when many other design parameters are held at constant values. Lastly, we identify efficient heterogeneous core designs by clustering per bench-mark optimal architectures. Collectively, these studies motivate the application of techniques in statistical inference for more effective use of modern simulator infrastructure.