Looking back on the language and hardware revolutions: measured power, performance, and scaling

  • Authors:

  • Hadi Esmaeilzadeh;Ting Cao;Yang Xi;Stephen M. Blackburn;Kathryn S. McKinley

  • Affiliations:

  • The University of Washington, Seattle, WA, USA;Australian National University, Canberra, Australia;Australian National University, Canberra, Australia;Australian National University, Canberra, Australia;The University of Texas at Austin, Austin, TX, USA

  • Venue:
  • Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
  • Year:
  • 2011

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Abstract

This paper reports and analyzes measured chip power and performance on five process technology generations executing 61 diverse benchmarks with a rigorous methodology. We measure representative Intel IA32 processors with technologies ranging from 130nm to 32nm while they execute sequential and parallel benchmarks written in native and managed languages. During this period, hardware and software changed substantially: (1) hardware vendors delivered chip multiprocessors instead of uniprocessors, and independently (2) software developers increasingly chose managed languages instead of native languages. This quantitative data reveals the extent of some known and previously unobserved hardware and software trends. Two themes emerge. (I) Workload: The power, performance, and energy trends of native workloads do not approximate managed workloads. For example, (a) the SPEC CPU2006 native benchmarks on the i7 (45) and i5 (32) draw significantly less power than managed or scalable native benchmarks; and (b) managed runtimes exploit parallelism even when running single-threaded applications. The results recommend architects always include native and managed workloads when designing and evaluating energy efficient hardware. (II) Architecture: Clock scaling, microarchitecture, simultaneous multithreading, and chip multiprocessors each elicit a huge variety of power, performance, and energy responses. This variety and the difficulty of obtaining power measurements recommends exposing on-chip power meters and when possible structure specific power meters for cores, caches, and other structures. Just as hardware event counters provide a quantitative grounding for performance innovations, power meters are necessary for optimizing energy.