Dynamic processors demand dynamic operating systems
HotPar'10 Proceedings of the 2nd USENIX conference on Hot topics in parallelism
Looking back on the language and hardware revolutions: measured power, performance, and scaling
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
Memory system performance in a NUMA multicore multiprocessor
Proceedings of the 4th Annual International Conference on Systems and Storage
Chameleon: operating system support for dynamic processors
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
What to make of multicore processors for reliable real-time systems?
Ada-Europe'10 Proceedings of the 15th Ada-Europe international conference on Reliable Software Technologies
Predictive power management for multi-core processors
ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
Power-aware performance increase via core/uncore reinforcement control for chip-multiprocessors
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Don't burn your mobile!: safe computational re-sprinting via model predictive control
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Accurate characterization of the variability in power consumption in modern mobile processors
HotPower'12 Proceedings of the 2012 USENIX conference on Power-Aware Computing and Systems
Assessing software interference management when modifying safety-related software
SAFECOMP'12 Proceedings of the 2012 international conference on Computer Safety, Reliability, and Security
Communications of the ACM
Portable performance on heterogeneous architectures
Proceedings of the eighteenth international conference on Architectural support for programming languages and operating systems
Multi-core scalability measurements: issues and solutions
PARA'12 Proceedings of the 11th international conference on Applied Parallel and Scientific Computing
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
Parallel algorithm for evolvable-based boolean synthesis on GPUs
Analog Integrated Circuits and Signal Processing
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The Intel® Core™ i7 processor code named Nehalem has a novel feature called Turbo Boost which dynamically varies the frequencies of the processor's cores. The frequency of a core is determined by core temperature, the number of active cores, the estimated power and the estimated current consumption. We perform an extensive analysis of the Turbo Boost technology to characterize its behavior in varying workload conditions. In particular, we analyze how the activation of Turbo Boost is affected by inherent properties of applications (i.e., their rate of memory accesses) and by the overall load imposed on the processor. Furthermore, we analyze the capability of Turbo Boost to mitigate Amdahl's law by accelerating sequential phases of parallel applications. Finally, we estimate the impact of the Turbo Boost technology on the overall energy consumption. We found that Turbo Boost can provide (on average) up to a 6% reduction in execution time but can result in an increase in energy consumption up to 16%. Our results also indicate that Turbo Boost sets the processor to operate at maximum frequency (where it has the potential to provide the maximum gain in performance) when the mapping of threads to hardware contexts is sub-optimal.