Genetic Algorithms and Machine Learning
Machine Learning
Ant Colony System for the Design of Combinational Logic Circuits
ICES '00 Proceedings of the Third International Conference on Evolvable Systems: From Biology to Hardware
A Genetic Programming Approach to Logic Function Synthesis by Means of Multiplexers
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
Prototyping with a Bio-Inspired Reconfigurable Chip
RSP '04 Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping
Genetic Programming and Evolvable Machines
Representations for Genetic and Evolutionary Algorithms
Representations for Genetic and Evolutionary Algorithms
Validity of the single processor approach to achieving large scale computing capabilities
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
Adaptive immune genetic algorithm for logic circuit design
Proceedings of the first ACM/SIGEVO Summit on Genetic and Evolutionary Computation
Evolvable Hardware: From Applications to Implications for the Theory of Computation
UC '09 Proceedings of the 8th International Conference on Unconventional Computation
Evaluation of the Intel® Core i7 Turbo Boost feature
IISWC '09 Proceedings of the 2009 IEEE International Symposium on Workload Characterization (IISWC)
Hardware accelerators for Cartesian genetic programming
EuroGP'08 Proceedings of the 11th European conference on Genetic programming
GPU-based island model for evolutionary algorithms
Proceedings of the 12th annual conference on Genetic and evolutionary computation
Developments in Cartesian Genetic Programming: self-modifying CGP
Genetic Programming and Evolvable Machines
Introduction to Evolutionary Computing
Introduction to Evolutionary Computing
Genetic Algorithm for Boolean minimization in an FPGA cluster
The Journal of Supercomputing
Evolving hardware by dynamically reconfiguring xilinx FPGAs
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
A flexible on-chip evolution system implemented on a xilinx Virtex-II pro device
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
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The use of evolutionary algorithms in the boolean synthesis is an attractive alternative to generate interesting and efficient hardware structures, with a high computational load. This paper presents the implementation of a parallel genetic programming (PGP) for boolean synthesis on a GPU-CPU based platform. Our implementation uses the island model, that allows the parallel and independent evolution of the PGP through the multiple processing units of the GPU and the multiple cores of a new generation desktop processors. We tested multiple mapping alternatives of the PGP on the platform in order to optimize the PGP response time. As a result we show that our approach achieves a speedup up to 41 compared to CPU implementation.