An evolvable hardware chip and its application as a multi-function prosthetic hand controller
AAAI '99/IAAI '99 Proceedings of the sixteenth national conference on Artificial intelligence and the eleventh Innovative applications of artificial intelligence conference innovative applications of artificial intelligence
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine
Genetic Programming and Evolvable Machines
ICES '00 Proceedings of the Third International Conference on Evolvable Systems: From Biology to Hardware
Prototyping a GA Pipeline for Complete Hardware Evolution
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
Bidirectional Incremental Evolution in Extrinsic Evolvable Hardware
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Towards the Automatic Design of More Efficient Digital Circuits
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Evolving multiplier circuits by training set and training vector partitioning
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Speeding up hardware evolution: a coprocessor for evolutionary algorithms
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Proceedings of the 3rd conference on Computing frontiers
Evolutionary functional recovery in virtual reconfigurable circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
An evolvable hardware system in Xilinx Virtex II Pro FPGA
International Journal of Innovative Computing and Applications
Advanced techniques for the creation and propagation of modules in cartesian genetic programming
Proceedings of the 10th annual conference on Genetic and evolutionary computation
An Online EHW Pattern Recognition System Applied to Face Image Recognition
Proceedings of the 2007 EvoWorkshops 2007 on EvoCoMnet, EvoFIN, EvoIASP,EvoINTERACTION, EvoMUSART, EvoSTOC and EvoTransLog: Applications of Evolutionary Computing
An online EHW pattern recognition system applied to sonar spectrum classification
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
An intrinsic evolvable hardware based on multiplexer module array
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Using systolic technique to accelerate an EHW engine for lossless image compression
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
Genetic Programming and Evolvable Machines
Complete FPGA implemented evolvable image filters
MICAI'06 Proceedings of the 5th Mexican international conference on Artificial Intelligence
High-Speed Reconfigurable Parallel System to Design Good Error Correcting Codes in Communications
Journal of Signal Processing Systems
Efficient phenotype evaluation in cartesian genetic programming
EuroGP'12 Proceedings of the 15th European conference on Genetic Programming
Parallel algorithm for evolvable-based boolean synthesis on GPUs
Analog Integrated Circuits and Signal Processing
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There have been introduced a number of systems with evolvable hardware on a single chip. To overcome the lack of flexibility in these systems, we propose a single-chip evolutionary system with the evolutionary algorithm implemented in software on a built-in processor. This architecture is implemented in a Xilinx Virtex-II Pro FPGA with an embedded PowerPC processor. This allows for a rapid processing of the time consuming parts in hardware and leaving other parts to more easily modifiable software. This platform will be beneficial for future work regarding both cost and compactness. Experiments have been performed on the physical device with software running in parallel with fitness computation in digital logic. The results show that the system uses only twice as much time when compared to a PC running at 10 times faster clock speed.