A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine
Genetic Programming and Evolvable Machines
A Hardware Implementation of a Genetic Programming System Using FPGAs and Handel-C
Genetic Programming and Evolvable Machines
A Pipelined Hardware Implementation of Genetic Programming Using FPGAs and Handel-C
EuroGP '02 Proceedings of the 5th European Conference on Genetic Programming
A massively parallel architecture for distributed genetic algorithms
Parallel Computing - Special issue: Parallel and nature-inspired computational paradigms and applications
Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey
Journal of VLSI Signal Processing Systems
Run-time reconfigurable systems for digital signal processing applications: a survey
Journal of VLSI Signal Processing Systems
Review: Neuromolecularware and its application to pattern recognition
Expert Systems with Applications: An International Journal
Genetic learning based fault tolerant models for digital systems
Applied Soft Computing
Genetic algorithm based routing method for efficient data transmission in sensor networks
ICIC'07 Proceedings of the intelligent computing 3rd international conference on Advanced intelligent computing theories and applications
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Using systolic technique to accelerate an EHW engine for lossless image compression
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Hardware accelerators for Cartesian genetic programming
EuroGP'08 Proceedings of the 11th European conference on Genetic programming
ICCSA'07 Proceedings of the 2007 international conference on Computational science and its applications - Volume Part III
Complete FPGA implemented evolvable image filters
MICAI'06 Proceedings of the 5th Mexican international conference on Artificial Intelligence
Packet classification with evolvable hardware hash functions – an intrinsic approach
BioADIT'06 Proceedings of the Second international conference on Biologically Inspired Approaches to Advanced Information Technology
Optimization of single variable functions using complete hardware evolution
Applied Soft Computing
A flexible on-chip evolution system implemented on a xilinx Virtex-II pro device
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
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In this paper a new approach to evolvable hardware is introduced termed "Complete Hardware Evolution" (CHE). This method differs from Extrinsic and Intrinsic evolution in that the evolution process itself is implemented in hardware. In addition, the evolution process implementation, referred to herein as the GA Pipeline, is implemented on the same chip as the evolving design. A prototype implementation of the GA Pipeline is presented which uses FPGA technology as the implementation medium.