A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine
Genetic Programming and Evolvable Machines
A Lossless Compression Method for Halftone Images Using Evolvable Hardware
ICES '01 Proceedings of the 4th International Conference on Evolvable Systems: From Biology to Hardware
Evolvable Hardware and Its Applications to Pattern Recognition and Fault-Tolerant Systems
Papers from an international workshop on Towards Evolvable Hardware, The Evolutionary Engineering Approach
Prototyping a GA Pipeline for Complete Hardware Evolution
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
GECCO '96 Proceedings of the 1st annual conference on Genetic and evolutionary computation
Towards intrinsic evolvable hardware for predictive lossless image compression
SEAL'06 Proceedings of the 6th international conference on Simulated Evolution And Learning
A flexible on-chip evolution system implemented on a xilinx Virtex-II pro device
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
Promises and challenges of evolvable hardware
IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
Automated synthesis of analog electrical circuits by means ofgenetic programming
IEEE Transactions on Evolutionary Computation
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The way combining intelligent technology with hardware technology to study real-world applications is one of the most important methodologies in the field of EHW. This paper designs a novel evolvable hardware engine for predictive lossless image compression in the perspective of hardware, and firstly implements the whole engine on reconfigurable hardware. As a result of the high-speed pipeline architecture, all the modules of this engine can process the data in parallel. For the most time-consuming fitness evaluation unit, the systolic array which essentially accelerate the fitness evaluation is employed. Experimental results show that the proposed evolvable hardware engine can reduce the computing time remarkably (the speedup ratio approximates to 500), and can fully utilize the hardware resources. The systolic technique adopted here also promises to scale up images size with comparatively slower speed of the increasing of the power consumption.