HGA: a hardware-based genetic algorithm
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
A Hardware Implementation of a Genetic Programming System Using FPGAs and Handel-C
Genetic Programming and Evolvable Machines
A Hardware Genetic Algorithm for the Travelling Salesman Problem on SPLASH 2
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Prototyping a GA Pipeline for Complete Hardware Evolution
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
Introduction to Evolvable Hardware: A Practical Guide for Designing Self-Adaptive Systems (IEEE Press Series on Computational Intelligence)
Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA
AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
FPGA Implementation of a Cellular Compact Genetic Algorithm
AHS '08 Proceedings of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems
A multilayer framework supporting autonomous run-time partial reconfiguration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Extrinsic evolvable hardware on the RISA architecture
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
High-speed FPGA-based implementations of a genetic algorithm
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Customizable FPGA IP core implementation of a general-purpose genetic algorithm engine
IEEE Transactions on Evolutionary Computation
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A genetic algorithm (GA) is a computer based search optimization technique that uses the Darwinian ''Theory of Evolution'' as a model for finding exact and approximate solutions. GAs belong to a large family of heuristic algorithms called evolutionary algorithms (EA) which are being increasingly utilized for solving complex optimization and search problems. The large computation time consumed by a GA implemented in software makes it unsuitable for real time applications. This hurdle is overcome by shifting the implementation to hardware, which drastically speeds up the time factor, thus presenting a scope for real time applications. This paper presents a complete hardware evolution (CHE) that is implemented on a single Field Programmable Gate Array (FPGA). An important advantage here is that, the knowledge of the proprietary configuration bit - stream's structure is not required. The hardware is used here for evaluating certain fitness functions and to evolve optimal solutions for single variable functions. A distinct feature of this CHE implementation is that an off-the-shelf FPGA is used without any other additional soft/hard ware support. The design uses five modules along with one memory module, totally constructed on the Configurable Logic Block (CLB) logic of the FPGA. The coding is done using VHDL and simulated using Xilinx ISE 9.1i. The Joint Test Action Group (JTAG) protocol is used to download the configuration bit stream to the FPGA. This hardware GA engine is evaluated with different chromosome lengths/selection methods/crossover methods. Compared with the previous implementations, an enhancement in speed, number of generations required for obtaining the optimal solution and area utilization is observed. The results have shown a shift from seconds to few nanoseconds when moving from software simulation to hardware implementation. Resource utilization for the different functions implemented varies from 0% to 94% approximately. A decrease of about 77.3% in the number of generations required to reach the global maxima is also witnessed.