Advanced techniques for the creation and propagation of modules in cartesian genetic programming
Proceedings of the 10th annual conference on Genetic and evolutionary computation
A Comparison of Evolvable Hardware Architectures for Classification Tasks
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
Implementation of a genetic algorithm on a virtex-ii pro FPGA
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
An online EHW pattern recognition system applied to sonar spectrum classification
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
High-speed FPGA-based implementations of a genetic algorithm
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Optimization of single variable functions using complete hardware evolution
Applied Soft Computing
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Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entirely hardware-based in order to increase the speed of the circuit evaluation which uses a large training set (360 images/23040 bytes). The fitness evaluation time for 1000 generations consisting of 16 individuals is 623ms, twice as fast as software fitness evaluation performed on a workstation running at a 30 times higher clock frequency. The rest of the genetic algorithm (GA) runs in software on a PowerPC 405 processor core on the FPGA. The total evolution time for 1000 generations is 1313ms, equivalent to the total time used by the workstation. Resource utilization for the fitness evaluation module is 1393 slices (10%) of a XC2VP30 device.