An online EHW pattern recognition system applied to sonar spectrum classification

Authors:
Kyrre Glette;Jim Torresen;Moritoshi Yasunaga
Affiliations:
University of Oslo, Department of Informatics, Oslo, Norway;University of Oslo, Department of Informatics, Oslo, Norway;University of Tsukuba, Graduate School of Systems and Information Engineering, Tsukuba, Ibaraki, Japan
Venue:
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Year:
2007

Citing 8
Cited 2

The application of genetic algorithms to the design of reconfigurable reasoning VLSI chips

FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Genetic Algorithms in Search, Optimization and Machine Learning

Genetic Algorithms in Search, Optimization and Machine Learning
Promises and Challenges of Evolvable Hardware

ICES '96 Proceedings of the First International Conference on Evolvable Systems: From Biology to Hardware
The Kernel-Adatron Algorithm: A Fast and Simple Learning Procedure for Support Vector Machines

ICML '98 Proceedings of the Fifteenth International Conference on Machine Learning
On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition

AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA

AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
Gene finding using evolvable reasoning hardware

ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
A flexible on-chip evolution system implemented on a xilinx Virtex-II pro device

ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware

Improving flexibility in on-line evolvable systems by reconfigurable computing

ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling

Microprocessors & Microsystems

Quantified Score

Hi-index	0.00

Visualization

Abstract

An evolvable hardware (EHW) system for high-speed sonar return classification has been proposed. The system demonstrates an average accuracy of 91.4% on a sonar spectrum data set. This is better than a feed-forward neural network and previously proposed EHW architectures. Furthermore, this system is designed for online evolution. Incremental evolution, data buses and high level modules have been utilized in order to make the evolution of the 480 bit-input classifier feasible. The classification has been implemented for a Xilinx XC2VP30 FPGA with a resource utilization of 81% and a classification time of 0.5µs.