The application of genetic algorithms to the design of reconfigurable reasoning VLSI chips

Authors:
Moritoshi Yasunaga;Jung Hwan Kim;Ikuo Yoshihara
Affiliations:
Institute of Information Sciences and Electronics, University of Tsukuba, Tsukuba, Ibaraki 305-8573, Japan;Center for Advanced Computer Studies, University of Louisiana, Lafayette, Louisiana;Cooperative Research Center, Miyazaki University
Venue:
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Year:
2000

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Abstract

In this paper, we present a new genetic-algorithm-based design methodology for reasoning VLSI chips, called as LoDETT (logic design with the evolved truth table). In LoDETT, each task's case database is transformed into truth tables, which are evolved to obtain generalization capability (i.e. rules behind the past cases) through genetic algorithms. Digital circuits are synthesized from the evolved truth-tables. Parallelism in each task can be embedded directly in the circuits by the direct hardware implementation of the case database. We applied LoDETT to the English pronunciation reasoning (EPR) problem, resulting in a GATalk chip. A GATalk chip has been designed with about 270K gates, and its reasoning time is about 100 ns for each phoneme. A prototype of the GATalk chip has been implemented using Xilinx XC4010 FPGA chips. It achieved a reasoning accuracy of 81.9% which is almost the same accuracy as NETTalk in neural networks and MBRTalk in parallel AI.