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Microprocessing and Microprogramming
The Ring Array Processor: a multiprocessing peripheral for connectionist applications
Journal of Parallel and Distributed Computing - Special issue on neural computing on massively parallel processing
Using and designing massively parallel computers for artificial neural networks
Journal of Parallel and Distributed Computing - Special issue on neural computing on massively parallel processing
SYNAPSE: a neurocomputer that synthesizes neural algorithms on a parallel systolic engine
Journal of Parallel and Distributed Computing - Special issue on neural computing on massively parallel processing
IEEE Micro
Experiences with non-numeric applications on multithreaded architectures
PPOPP '97 Proceedings of the sixth ACM SIGPLAN symposium on Principles and practice of parallel programming
Computer Vision Algorithms on Reconfigurable Logic Arrays
IEEE Transactions on Parallel and Distributed Systems
The application of genetic algorithms to the design of reconfigurable reasoning VLSI chips
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Evolvable Reasoning Hardware: Its Prototyping and Performance Evaluation
Genetic Programming and Evolvable Machines
Parallel Algorithms for the Training Process of a Neural Network-Based System
International Journal of High Performance Computing Applications
Modeling of feedforward neural network in PAHRA architecture
SMO'09 Proceedings of the 9th WSEAS international conference on Simulation, modelling and optimization
Accelerating large-scale convolutional neural networks with parallel graphics multiprocessors
ICANN'10 Proceedings of the 20th international conference on Artificial neural networks: Part III
Suitability of two associative memory neural networks to character recognition
AI'04 Proceedings of the 17th Australian joint conference on Advances in Artificial Intelligence
SETN'12 Proceedings of the 7th Hellenic conference on Artificial Intelligence: theories and applications
Parallel and local learning for fast probabilistic neural networks in scalable data mining
Proceedings of the 6th Balkan Conference in Informatics
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Neural computation means organizing processing into a number of processing elements that are massively interconnected and that exchange signals. Processing within elements usually involves adding weighted input values, applying a (non)linear function to the input sum, and forwarding the result to other elements. Since the basic principle of neurocomputation is learning by example, such processing must be repeated again and again, with weights being changed until a network learns the problem. An artificial neural network can be implemented as a simulation programmed on a general-purpose computer or as an emulation realized on special-purpose hardware. Although sequential simulations are widespread and offer comfortable software environments for developing and analyzing neural networks, the computational needs of realistic applications exceed the capabilities of sequential computers. Parallelization was therefore necessary to cope with the high computational and communication demands of neuro-applications. As matrix-vector operations are at the core of many neuroalgorithms, processing is often organized in such a way as to ensure their efficient implementation. The first implementations were exercised on general-purpose parallel machines. When they approached the performance limits of standard supercomputers, the research focus shifted to architectural improvements. One approach was to build general-purpose programmable neurohardware; another was to construct special-purpose neurohardware that emulates a particular neuromodel. This article discusses techniques and means for parallelizing neurosimulations, both at a high programming level and at a low hardware-emulation level.