Communications of the ACM - Special issue on parallelism
Introduction to statistical pattern recognition (2nd ed.)
Introduction to statistical pattern recognition (2nd ed.)
Massively parallel artificial intelligence
Massively parallel artificial intelligence
Simulating Artificial Neural Networks on Parallel Architectures
Computer - Special issue: neural computing: companion issue to Spring 1996 IEEE Computational Science & Engineering
Neural Networks for Pattern Recognition
Neural Networks for Pattern Recognition
Field-Programmable Gate Arrays
IEEE Design & Test
Gene finding using evolvable reasoning hardware
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
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In this paper, we propose evolvable reasoning hardware and its design methodology. In the proposed design methodology, case databases of each reasoning task are transformed into truth tables, which are evolved to extract rules behind the past cases through a genetic algorithm. Circuits for the evolvable reasoning hardware are synthesized from the evolved truth-tables. Parallelism in each task can be embedded directly in the circuits through the direct hardware implementation of the case databases. We developed the evolvable reasoning hardware prototype using Xilinx Virtex FPGA chips and applied it to the English-pronunciation-reasoning (EPR) task. The evolvable reasoning hardware for the EPR task was implemented with 270K gates, achieving an extremely high reasoning speed of less than 300 ns/phoneme. It also achieved a reasoning accuracy of 82.1% which is almost the same accuracy as NETTalk in neural networks and MBRTalk in parallel AI.