Using and designing massively parallel computers for artificial neural networks

Simulating Artificial Neural Networks on Parallel Architectures

Computer - Special issue: neural computing: companion issue to Spring 1996 IEEE Computational Science & Engineering

Computer Vision Algorithms on Reconfigurable Logic Arrays

IEEE Transactions on Parallel and Distributed Systems

Mixed-Mode Programmable and Scalable Architecture for On-Chip Learning

Analog Integrated Circuits and Signal Processing - Special issue on Learning on Silicon

Parallel Implementation of Self-Organizing Map on the Partial Tree Shape Neurocomputer

Neural Processing Letters

Parallel implementation of self-organizing maps

Self-Organizing neural networks

A Distributed Framework for Parallel Data Mining Using HPJava

BT Technology Journal

Efficient Mapping of ANNs on Hypercube Massively Parallel Machines

IEEE Transactions on Computers

Massively distributed digital implementation of an integrate-and-fire LEGION network for visual scene segmentation

Neurocomputing

Challenges for large-scale implementations of spiking neural networks on FPGAs

Neurocomputing

VCluster: a thread-based Java middleware for SMP and heterogeneous clusters with thread migration support

Software—Practice & Experience

Exploiting training example parallelism with a batch variant of the ART 2 classification algorithm

PDCN '08 Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks

LambdaRank acceleration for relevance ranking in web search engines (abstract only)

Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays

A development environment for multilayer neural network applications mapped onto DSPs with multiprocessing capabilities

VECPAR'02 Proceedings of the 5th international conference on High performance computing for computational science

An FPGA-based accelerator for LambdaRank in Web search engines

ACM Transactions on Reconfigurable Technology and Systems (TRETS)

A 32-bit binary floating point neuro-chip

ICNC'05 Proceedings of the First international conference on Advances in Natural Computation - Volume Part III

A scalable pipelined architecture for real-time computation of MLP-BP neural networks

Microprocessors & Microsystems

Neural computation in medicine

Artificial Intelligence in Medicine

A new classification approach for neural networks hardware: from standards chips to embedded systems on chip

Artificial Intelligence Review