Parallel distributed processing: explorations in the microstructure of cognition, vol. 1: foundations
Using and designing massively parallel computers for artificial neural networks
Journal of Parallel and Distributed Computing - Special issue on neural computing on massively parallel processing
Tree-based special-purpose array architectures for neural computing
Journal of VLSI Signal Processing Systems
FPGA Implementation of a Pipelined On-Line Backpropagation
Journal of VLSI Signal Processing Systems
FPGA Implementations of Neural Networks
FPGA Implementations of Neural Networks
Artificial neural networks: a review of commercial hardware
Engineering Applications of Artificial Intelligence
A mixed hardware-software approach to flexible artificial neural network training on FPGA
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
A digital architecture for support vector machines: theory, algorithm, and FPGA implementation
IEEE Transactions on Neural Networks
Analog and digital FPGA implementation of BRIN for optimization problems
IEEE Transactions on Neural Networks
Simultaneous perturbation learning rule for recurrent neural networks and its FPGA implementation
IEEE Transactions on Neural Networks
Real-time learning capability of neural networks
IEEE Transactions on Neural Networks
The Impact of Arithmetic Representation on Implementing MLP-BP on FPGAs: A Study
IEEE Transactions on Neural Networks
Performance analysis of a pipelined backpropagation parallel algorithm
IEEE Transactions on Neural Networks
Fast neural net simulation with a DSP processor array
IEEE Transactions on Neural Networks
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In this paper a novel architecture for implementing multi-layer perceptron (MLP) neural networks on field programmable gate arrays (FPGA) is presented. The architecture presents a new scalable design that allows variable degrees of parallelism in order to achieve the best balance between performance and FPGA resources usage. Performance is enhanced using a highly efficient pipelined design. Extensive analysis and simulations have been conducted on four standard benchmark problems. Results show that a minimum performance boost of three orders of magnitude (O^3) over software implementation is regularly achieved. We report performance of 2-67GCUPS for these simple problems, and performance reaching over 1TCUPS for larger networks and different single FPGA chips. To our knowledge, this is the highest speed reported to date for any MLP network implementation on FPGAs.