Offline Geometric Parameters for Automatic Signature Verification Using Fixed-Point Arithmetic
IEEE Transactions on Pattern Analysis and Machine Intelligence
Efficient Implementation of SVM Training on Embedded Electronic Systems
WILF '07 Proceedings of the 7th international workshop on Fuzzy Logic and Applications: Applications of Fuzzy Sets Theory
A support vector machine with integer parameters
Neurocomputing
FPGA Implementation of Support Vector Machines for 3D Object Identification
ICANN '09 Proceedings of the 19th International Conference on Artificial Neural Networks: Part I
Diagnosis of ADHD using SVM algorithm
Proceedings of the Third Annual ACM Bangalore Conference
An on-chip-trainable Gaussian-Kernel analog support vector machine
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Signature classification using optimum contour
ACS'06 Proceedings of the 6th WSEAS international conference on Applied computer science
Nonlinear channel equalization using concurrent support vector machine processor
ISNN'06 Proceedings of the Third international conference on Advances in Neural Networks - Volume Part III
Nature inspiration for support vector machines
KES'06 Proceedings of the 10th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part II
A scalable pipelined architecture for real-time computation of MLP-BP neural networks
Microprocessors & Microsystems
On-line fast palmprint identification based on adaptive lifting wavelet scheme
Knowledge-Based Systems
K-means clustering algorithm for multimedia applications with flexible HW/SW co-design
Journal of Systems Architecture: the EUROMICRO Journal
VLSI design of an SVM learning core on sequential minimal optimization algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we propose a digital architecture for support vector machine (SVM) learning and discuss its implementation on a field programmable gate array (FPGA). We analyze briefly the quantization effects on the performance of the SVM in classification problems to show its robustness, in the feedforward phase, respect to fixed-point math implementations; then, we address the problem of SVM learning. The architecture described here makes use of a new algorithm for SVM learning which is less sensitive to quantization errors respect to the solution appeared so far in the literature. The algorithm is composed of two parts: the first one exploits a recurrent network for finding the parameters of the SVM; the second one uses a bisection process for computing the threshold. The architecture implementing the algorithm is described in detail and mapped on a real current-generation FPGA (Xilinx Virtex II). Its effectiveness is then tested on a channel equalization problem, where real-time performances are of paramount importance.