VLSI design of an SVM learning core on sequential minimal optimization algorithm

Authors:
Ta-Wen Kuan;Jhing-Fa Wang;Jia-Ching Wang;Po-Chuan Lin;Gaung-Hui Gu
Affiliations:
Department Electrical Engineering, National Cheng-Kung University, Tainan, Taiwan;Department Electrical Engineering, National Cheng-Kung University, Tainan, Taiwan;Department of Computer Science and Information Engineering, National Central University, Jhongli, Taiwan;Multimedia and Embedded System Design Laboratory, Department of Electronics Engineering and Computer Science, Tung-Fang Institute of Technology, Kaohsiung, Taiwan;Industrial Technology Research Institute, Hsinchu, Taiwan
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2012

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Abstract

The sequential minimal optimization (SMO) algorithm has been extensively employed to train the support vector machine (SVM). This work presents an efficient application specific integrated circuit chip design for sequential minimal optimization. This chip is implemented as an intellectual property core, suitable for use in an SVM-based recognition system on a chip. The proposed SMO chip was tested and found to be fully functional, using a prototype system based on the Altera DE2 board with a Cyclone II 2C70 field-programmable gate array.