Support vector machine-based image classification for genetic syndrome diagnosis
Pattern Recognition Letters
EURASIP Journal on Advances in Signal Processing - Special issue on signal processing advances in robots and autonomy
Current-Mode Computation with Noise in a Scalable and Programmable Probabilistic Neural VLSI System
ICANN '09 Proceedings of the 19th International Conference on Artificial Neural Networks: Part I
Minimising Contrastive Divergence with Dynamic Current Mirrors
ICANN '09 Proceedings of the 19th International Conference on Artificial Neural Networks: Part I
Ensemble for high recognition performance FPGA
SMC'09 Proceedings of the 2009 IEEE international conference on Systems, Man and Cybernetics
Hibernets: energy-efficient sensor networks using analog signal processing
Proceedings of the 9th ACM/IEEE International Conference on Information Processing in Sensor Networks
An on-chip-trainable Gaussian-Kernel analog support vector machine
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Nonlinear channel equalization using concurrent support vector machine processor
ISNN'06 Proceedings of the Third international conference on Advances in Neural Networks - Volume Part III
Benchmarking data mining methods in CAT
ICIC'11 Proceedings of the 7th international conference on Advanced Intelligent Computing Theories and Applications: with aspects of artificial intelligence
Real-Time on-line-learning support vector machine based on a fully-parallel analog VLSI processor
ICAISC'12 Proceedings of the 11th international conference on Artificial Intelligence and Soft Computing - Volume Part II
On-line fast palmprint identification based on adaptive lifting wavelet scheme
Knowledge-Based Systems
K-means clustering algorithm for multimedia applications with flexible HW/SW co-design
Journal of Systems Architecture: the EUROMICRO Journal
VLSI design of an SVM learning core on sequential minimal optimization algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Detection of complex objects in streaming video poses two fundamental challenges: training from sparse data with proper generalization across variations in the object class and the environment; and the computational power required of the trained classifier running real-time. The Kerneltron supports the generalization performance of a support vector machine (SVM) and offers the bandwidth and efficiency of a massively parallel architecture. The mixed-signal very large-scale integration (VLSI) processor is dedicated to the most intensive of SVM operations: evaluating a kernel over large numbers of vectors in high dimensions. At the core of the Kerneltron is an internally analog, fine-grain computational array performing externally digital inner-products between an incoming vector and each of the stored support vectors. The three-transistor unit cell in the array combines single-bit dynamic storage, binary multiplication, and zero-latency analog accumulation. Precise digital outputs are obtained through oversampled quantization of the analog array outputs combined with bit-serial unary encoding of the digital inputs. The 256 input, 128 vector Kerneltron measures 3 mm×3mm in 0.5 μm CMOS, delivers 6.5 GMACS throughput at 5.9 mW power, and attains 8-bit output resolution.