An implementation of network learning on the Connection Machine
Connectionist models and their implications: readings from cognitive science
Learning internal representations by error propagation
Parallel distributed processing: explorations in the microstructure of cognition, vol. 1
Algorithmic mapping of neural network Models onto Parallel SIMD Machines
IEEE Transactions on Computers - Special issue on artificial neural networks
Programmable active memories: reconfigurable systems come of age
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computer architecture: single and parallel systems
Computer architecture: single and parallel systems
Artificial Neural Network Implementation on a Fine-Grained FPGA
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
A Fast FPGA Implementation of a General Purpose Neuron
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
Function Evaluation by Table Look-up and Addition
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
On-Chip Backpropagation Training Using Parallel Stochastic Bit Streams
MICRONEURO '96 Proceedings of the 5th International Conference on Microelectronics for Neural Networks and Fuzzy Systems
Building a 2D-Compatible Multilayer Neural Network
IJCNN '00 Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN'00)-Volume 2 - Volume 2
Implementing regularly structured neural networks on the DREAM machine
IEEE Transactions on Neural Networks
Backpropagation in linear arrays-a performance analysis and optimization
IEEE Transactions on Neural Networks
A dynamically configurable coprocessor for convolutional neural networks
Proceedings of the 37th annual international symposium on Computer architecture
A scalable pipelined architecture for real-time computation of MLP-BP neural networks
Microprocessors & Microsystems
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The paper describes the implementation of a systolic array for a multilayer perceptron with a hardware-friendly learning algorithm. A pipelined modification of the on-line backpropagation algorithm is shown and explained. It better exploits the parallelism because both the forward and backward phases can be performed simultaneously. The neural network performance for the proposed modification is discussed and compared with the standard so-called on-line backpropagation algorithm in typical databases and with the various precisions required. Although the preliminary results are positive, subsequent theoretical analysis and further experiments with different training sets will be necessary. For this reason our VLSI systolic architecture--together with the combination of FPGA reconfiguration properties and a design flow based on generic VHDL--can create a reusable, flexible, and fast method of designing a complete ANN on a single FPGA and can permit very fast hardware verifications for our trials of the Pipeline On-line Backpropagation algorithm and the standard algorithms.