High-energy physics on DECPeRLe-1 programmable active memory
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
The Transmogrifier-2: a 1 million gate rapid prototyping system
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Power optimization for FPGA look-up tables
Proceedings of the 1997 international symposium on Physical design
A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Kestrel: A Programmable Array for Sequence Analysis
Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
A reconfigurable arithmetic array for multimedia applications
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Memory interfacing and instruction specification for reconfigurable processors
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Multi-terminal net routing for partial crossbar-based multi-FPGA systems
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Configuration caching vs data caching for striped FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers
IEEE Transactions on Computers
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Reconfigurable computing: what, why, and implications for design automation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Hardware compilation for FPGA-based configurable computing machines
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors
IEEE Transactions on Computers
Artificial neural network implementation on a single FPGA of a pipelined on-line backpropagation
ISSS '00 Proceedings of the 13th international symposium on System synthesis
High-Radix Montgomery Modular Exponentiation on Reconfigurable Hardware
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Adaptive interfacing with reconfigurable computers
ACSAC '01 Proceedings of the 6th Australasian conference on Computer systems architecture
A SAT Solver Using Reconfigurable Hardware and Virtual Logic
Journal of Automated Reasoning
Reconfigurable Computing for Digital Signal Processing: A Survey
Journal of VLSI Signal Processing Systems
Designing Run-Time Reconfigurable Systems with JHDL
Journal of VLSI Signal Processing Systems
A new approach to pose detection using a trinocular stereovision system
Real-Time Imaging
Designing and Debugging Custom Computing Applications
IEEE Design & Test
A Polymorphous Computing Fabric
IEEE Micro
An evolutionary approach to dynamic task scheduling on FPGAs with restricted buffer
Journal of Parallel and Distributed Computing - Problems in parallel and distributed computing: Solutions based on evolutionary paradigms
ATLANTIS - A Hybrid FPGA/RISC Based Re-configurable System
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Finite Digital Synchronous Circuits Are Characterized by 2-Algebraic Truth Tables
ASIAN '00 Proceedings of the 6th Asian Computing Science Conference on Advances in Computing Science
Compiler Optimizations for Adaptive EPIC Processors
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
Efficient Addition on Field Programmable Gate Arrays
FST TCS '01 Proceedings of the 21st Conference on Foundations of Software Technology and Theoretical Computer Science
Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Loop Tiling for Reconfigurable Accelerators
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Multiterminal net routing for partial crossbar-based multi-FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Journal of Systems Architecture: the EUROMICRO Journal
Configurable computing: the catalyst for high-performance architectures
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Kestrel: Design of an 8-bit SIMD Parallel Processor
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Architecture Design of Reconfigurable Pipelined Datapaths
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Debugging Techniques for Dynamically Reconfigurable Hardware
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A CAD Suite for High-Performance FPGA Design
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Dynamic Precision Management for Loop Computations on Reconfigurable Architectures
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Parallelizing Applications into Silicon
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Run time reconfiguration of FPGA for scanning genomic databases
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Flexible image acquisition using reconfigurable hardware
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Polymorphous fabric-based systems: model, tools, applications
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Using reconfigurability to achieve real-time profiling for hardware/software codesign
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
Efficient metrics and high-level synthesis for dynamically reconfigurable logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems
IEEE Transactions on Computers
Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey
Journal of VLSI Signal Processing Systems
FPGA Implementation of a Pipelined On-Line Backpropagation
Journal of VLSI Signal Processing Systems
Run-time reconfigurable systems for digital signal processing applications: a survey
Journal of VLSI Signal Processing Systems
Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Finding the Next Computational Model: Experience with the UCSC Kestrel
Journal of Signal Processing Systems
Design, Debug, Deploy: The Creation of Configurable Computing Applications
Journal of Signal Processing Systems
A single layer architecture to FPGA implementation of BP artificial neural network
CAR'10 Proceedings of the 2nd international Asia conference on Informatics in control, automation and robotics - Volume 2
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
An architect's workbench for reconfigurable computing
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
ACM SIGARCH Computer Architecture News
Mesh routing topologies for multi-FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect estimation for mesh-based reconfigurable computing
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
Design and analysis of adaptive processor
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Embedded Systems Design
Policy-driven memory protection for reconfigurable hardware
ESORICS'06 Proceedings of the 11th European conference on Research in Computer Security
FPGA implementation of particle swarm optimization for Bayesian network learning
Computers and Electrical Engineering
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Programmable active memories (PAM) are a novel form of universal reconfigurable hardware coprocessor. Based on field-programmable gate array (FPGA) technology, a PAM is a virtual machine, controlled by a standard microprocessor, which can be dynamically and indefinitely reconfigured into a large number of application-specific circuits. PAM's offer a new mixture of hardware performance and software versatility. We review the important architectural features of PAM's, through the example of DECPeRLe-1, an experimental device built in 1992. PAM programming is presented, in contrast to classical gate-array and full custom circuit design. Our emphasis is on large, code-generated synchronous systems descriptions; no compromise is made with regard to the performance of the target circuits. We exhibit a dozen applications where PAM technology proves superior, both in performance and cost, to every other existing technology, including supercomputers, massively parallel machines, and conventional custom hardware. The fields covered include computer arithmetic, cryptography, error correction, image analysis, stereo vision, video compression, sound synthesis, neural networks, high-energy physics, thermodynamics, biology and astronomy. At comparable cost, the computing power virtually available in a PAM exceeds that of conventional processors by a factor 10 to 1000, depending on the specific application, in 1992. A technology shrink increases the performance gap between conventional processors and PAM's. By Noyce's law, we predict by how much the performance gap will widen with time.