Placement of Linear Arrays

Authors:
Erwan Fabiani;Dominique Lavenier
Affiliations:
-;-
Venue:
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Year:
2000

Citing 2
Cited 1

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Placing, Routing, and Editing Virtual FPGAs

FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications

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Abstract

This paper presents a methodology for mapping linear processor arrays onto FPGA components. By taking advantage of regularity and locality properties of these structures, a placement is pre-defined, allowing vendor tools to skip this phase and produce fast and optimized routing.