CATHEDRAL II—a computer-aided synthesis system for digital signal processing VLSI systems
Computer-Aided Engineering Journal
Building and Using a Highly Parallel Programmable Logic Array
Computer - Special issue on experimental research in computer architecture
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
High level synthesis and generating FPGAs with the BEDROC system
Journal of VLSI Signal Processing Systems - Special issue on field-programmable gate arrays
An architecture for a DSP field-programmable gate array
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Programmable active memories: reconfigurable systems come of age
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Signal processing at 250 MHz using high-performance FPGA's
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Wormhole run-time reconfiguration
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
A programming environment for the design of complex high speed ASICs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Digital systems engineering
Configuration cloning: exploiting regularity in dynamic DSP architectures
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
A reconfigurable arithmetic array for multimedia applications
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
PipeRench: a co/processor for streaming multimedia acceleration
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Software environment for a multiprocessor DSP
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Tolerating operational faults in cluster-based FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Spectrum
Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System
Journal of VLSI Signal Processing Systems
Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead
Journal of VLSI Signal Processing Systems
A Model and Methodology for Hardware-Software Codesign
IEEE Design & Test
Applying an XC6200 to Real-Time Image Processing
IEEE Design & Test
Compiler Architectures for Heterogeneous Systems
LCPC '95 Proceedings of the 8th International Workshop on Languages and Compilers for Parallel Computing
Use of Reconfigurability in Variable-Length Code Detection at Video Rates
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Real-time stereo vision on the PARTS reconfigurable computer
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A dynamic reconfiguration run-time system
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Increased FPGA capacity enables scalable, flexible CCMs: an example from image processing
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Mapping applications to the RaPiD configurable architecture
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Automated target recognition on SPLASH 2
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Hardware/Software Integration in Solar Polarimetry
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A Run-Time Reconfigurable Engine for Image Interpolation
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A Re-evaluation of the Practicality of Floating-Point Operations on FPGAs
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
An Overview of the COBRA-ABS High Level Synthesis System for Multi-FPGA Systems
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
New FPGA Architecture for Bit-Serial Pipeline Datapath
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Accelerating Adobe Photoshop with the Reconfigurable Logic
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Automating Production of Run-Time Reconfigurable Designs
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Configuration Compression for the Xilinx XC6200 FPGA
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Parallelizing Applications into Silicon
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Incremental Compilation for Logic Emulation
RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
Teramac-configurable custom computing
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Flexible image acquisition using reconfigurable hardware
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Quantitative analysis of floating point arithmetic on FPGA based custom computing machines
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Dynamic algorithm transforms for low-power reconfigurable adaptiveequalizers
IEEE Transactions on Signal Processing
Logic emulation with virtual wires
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Video communications using rapidly reconfigurable hardware
IEEE Transactions on Circuits and Systems for Video Technology
A dynamically reconfigurable adaptive viterbi decoder
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Journal of VLSI Signal Processing Systems
Energy-efficient signal processing using FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering
PACS '00 Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers
Processor Architectures for Multimedia Applications
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
Processor architectures for multimedia applications
Embedded processor design challenges
A Flexible and Energy-Efficient Coarse-Grained Reconfigurable Architecture for Mobile Systems
The Journal of Supercomputing
Journal of VLSI Signal Processing Systems
A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing
Journal of VLSI Signal Processing Systems
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
Reconfigurable Hardware SAT Solvers: A Survey of Systems
IEEE Transactions on Computers
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip
Journal of VLSI Signal Processing Systems
Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey
Journal of VLSI Signal Processing Systems
Domain Specific Reconfigurable Processing Core Architecture for Digital Filtering Applications
Journal of VLSI Signal Processing Systems
H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Temporal floorplanning using the T-tree formulation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Run-time reconfigurable systems for digital signal processing applications: a survey
Journal of VLSI Signal Processing Systems
Design and Implementation of Flexible Resampling Mechanism for High-Speed Parallel Particle Filters
Journal of VLSI Signal Processing Systems
Reconfigurable Coprocessor for Multimedia Application Domain
Journal of VLSI Signal Processing Systems
Flexible Controller Design and Its Application for Concurrent Execution of Buffer Centric Dataflows
Journal of VLSI Signal Processing Systems
Temporal floorplanning using the three-dimensional transitive closure subGraph
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The Chameleon architecture for streaming DSP applications
EURASIP Journal on Embedded Systems
Examining the viability of FPGA supercomputing
EURASIP Journal on Embedded Systems
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
A configurable fractionally-spaced blind adaptive equalizer for QAM demodulators
Digital Signal Processing
Dynamic image filter selection using partially reconfigurable FPGAs for imaging operations
CSECS'06 Proceedings of the 5th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing
ACM Transactions on Embedded Computing Systems (TECS)
Hybrid Pipeline Structure for Self-Organizing Learning Array
ISNN '07 Proceedings of the 4th international symposium on Neural Networks: Part II--Advances in Neural Networks
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Formalization of data flow computing and a coinductive approach to verifying flowware synthesis
Transactions on computational science I
A Simulation Framework for Rapid Analysis of Reconfigurable Computing Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
EURASIP Journal on Advances in Signal Processing
Journal of Signal Processing Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Platform-aware bottleneck detection for reconfigurable computing applications
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Efficient resource sharing architecture for multistandard communication system
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
ACM SIGARCH Computer Architecture News
Image processing with CNN in a FPGA-Based augmented reality system for visually impaired people
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
Ambient Intelligence in Everyday Life
ACM SIGARCH Computer Architecture News
QUKU: A dual-layer reconfigurable architecture
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Dynamically reconfigurable entropy coder for multi-standard video adaptation using FaRM
Microprocessors & Microsystems
An FPGA-based parallel processor for black-scholes option pricing using finite differences schemes
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Design space exploration for partially reconfigurable architectures in real-time systems
Journal of Systems Architecture: the EUROMICRO Journal
A Reconfigurable Parallel Hardware Implementation of the Self-Tuning Regulator
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
| Hi-index | 0.00 |
Steady advances in VLSI technology and design tools have extensively expanded the application domain of digital signal processing over the past decade. While application-specific integrated circuits (ASICs) and programmable digital signal processors (PDSPs) remain the implementation mechanisms of choice for many DSP applications, increasingly new system implementations based on reconfigurable computing are being considered. These flexible platforms, which offer the functional efficiency of hardware and the programmability of software, are quickly maturing as the logic capacity of programmable devices follows Moore's Law and advanced automated design techniques become available. As initial reconfigurable technologies have emerged, new academic and commercial efforts have been initiated to support power optimization, cost reduction, and enhanced run-time performance.This paper presents a survey of academic research and commercial development in reconfigurable computing for DSP systems over the past fifteen years. This work is placed in the context of other available DSP implementation media including ASICs and PDSPs to fully document the range of design choices available to system engineers. It is shown that while contemporary reconfigurable computing can be applied to a variety of DSP applications including video, audio, speech, and control, much work remains to realize its full potential. While individual implementations of PDSP, ASIC, and reconfigurable resources each offer distinct advantages, it is likely that integrated combinations of these technologies will provide more complete solutions.