Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Reconfigurable Computing for Digital Signal Processing: A Survey
Journal of VLSI Signal Processing Systems
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Configuration bitstream compression for dynamically reconfigurable FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A new approach to compress the configuration information of programmable devices
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
A Programmable Bitstream Parser for Multiple Video Coding Standards
ICICIC '06 Proceedings of the First International Conference on Innovative Computing, Information and Control - Volume 3
Ultra-Fast Downloading of Partial Bitstreams through Ethernet
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
Dynamic replacement of video coding elements
Image Communication
Towards rapid dynamic partial reconfiguration in video-based driver assistance systems
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
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Dynamic and Partial Reconfiguration (DPR) is a feature present in modern Xilinx FPGAs, bringing flexibility to a whole new level. However, it is not yet wide spread in the industry because of poor performance and a lack of a cost model to estimate a solution early in the design process. In this paper, we present our methodology for developing systems capable of dynamic and partial reconfiguration with strict real-time constraints. Our approach is based on FaRM (Fast Reconfiguration Manager), a high-speed controller reaching the configuration port theoretical throughput in Xilinx FPGAs. FaRM performance is estimated using a cost model, which allows us to determine the optimum FIFO size to satisfy timing constraints with the best resources trade-off. We validate our approach with a video application that should be able to encode an H.264 (HD) and an MPEG-2 (SD) stream at the same time. For this we used two entropy encoders on the same reconfigurable zone, while satisfying constraints determined by the video streams. This is the first step of a fully reconfigurable video adaptation system. We also present our unified reconfigurable zone interfaces, specific to video adaptation.