On-Road Vehicle Detection: A Review
IEEE Transactions on Pattern Analysis and Machine Intelligence
Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Ultra-Fast Downloading of Partial Bitstreams through Ethernet
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Run-time generation of partial FPGA configurations
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Signal Processing Systems
On the Evolution of Hardware Circuits via Reconfigurable Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Dynamically reconfigurable entropy coder for multi-standard video adaptation using FaRM
Microprocessors & Microsystems
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Using dynamically reconfigurable hardware is useful especially when a high degree of flexibility is demanded and the application requires inherent parallelism to achieve real-time constraints. Depending on various driving conditions different algorithms have to be used for video processing. These different algorithms require different hardware accelerator engines, which are loaded into the AutoVision chip at run-time of the system. The novelties presented in this paper are the determination of the maximum frequency for dynamic partial reconfiguration of Xilinx Virtex-II Pro, Virtex-4 and Virtex-5 devices and a modified overclocked version of the ICAP controller. In addition an online verification approach is presented that can determine configuration errors that might be caused by configuring a device above the specified frequencies. This results in a reconfiguration throughput which is three times higher than the maximum throughput specified by Xilinx.