Improving functional density using run-time circuit reconfiguration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 1st conference on Computing frontiers
The MOLEN Polymorphic Processor
IEEE Transactions on Computers
The Molen compiler for reconfigurable processors
ACM Transactions on Embedded Computing Systems (TECS)
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer
Journal of VLSI Signal Processing Systems
Proceedings of the conference on Design, automation and test in Europe
Towards software defined radios using coarse-grained reconfigurable hardware
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Secure Content Delivery System Based on a Partially Reconfigurable FPGA
IEICE - Transactions on Information and Systems
IDEA and AES, two cryptographic algorithms implemented using partial and dynamic reconfiguration
Microelectronics Journal
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
A new methodology to implement the AES algorithm using partial and dynamic reconfiguration
Integration, the VLSI Journal
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
Runtime Temporal Partitioning Assembly to Reduce FPGA Reconfiguration Time
RECONFIG '09 Proceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs
New OPBHWICAP Interface for Realtime Partial Reconfiguration of FPGA
RECONFIG '09 Proceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs
A 10 Gbps OTN Framer Implementation Targeting FPGA Devices
RECONFIG '09 Proceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs
Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications
Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications
VAPRES: a virtual architecture for partially reconfigurable embedded systems
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Dynamic Reconfiguration Optimisation with Streaming Data Decompression
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
Fingerprint image processing acceleration through run-time reconfigurable hardware
IEEE Transactions on Circuits and Systems II: Express Briefs
Towards rapid dynamic partial reconfiguration in video-based driver assistance systems
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Biometrics-based consumer applications driven by reconfigurable hardware architectures
Future Generation Computer Systems
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Day after day, embedded systems add more compute-intensive applications inside their end products: cryptography or image and video processing are some examples found in leading markets like consumer electronics and automotive. To face up these ever-increasing computational demands, the use of hardware accelerators synthesized in field-programmable gate arrays (FPGA) lets achieve processing speedups of orders of magnitude versus their counterpart CPU-based software approaches. However, the inherent increment in physical resources penalizes in cost. To address this issue, dynamically reconfigurable hardware technology definitively reached its maturity. SRAM-based reconfigurable logic goes beyond the classical conception of static hardware resources distributed in space and held invariant for the entire application life cycle; it provides a new design abstraction featured by the temporal partitioning of such resources to promote their continuous reuse, reconfiguring them on the fly to play a different role in each instant. This new computing paradigm lets balance the design of embedded applications by partitioning their functionality in space and time--through a series of mutually-exclusive processing tasks synthesized multiplexed in time on the same set of resources--and achieving thus cost savings in both area and power metrics. However, the exploitation of this system versatility requires special attention to avoid performance degradation. Such technical aspects are addressed in this work intended to be a survey on reconfigurable hardware technology and aimed at defining an open, standard and cost-effective system architecture driven by flexible coprocessors instantiated on demand on reconfigurable resources of an FPGA. This concept fits well with the functional features demanded to many embedded applications today and its feasibility has been proved with a state-of-the-art commercial SRAM-based FPGA platform. The achieved results highlight dynamic partial reconfiguration as a potential technology to lead the next computing wave in the industry.