Journal of Signal Processing Systems
Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
FPGA bitstream compression and decompression using LZ and golomb coding (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
UPaRC: ultra-fast power-aware reconfiguration controller
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Journal of Real-Time Image Processing
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This paper presents a high performance reconfiguration controller enhanced with the use of streaming lossless decompression in its data path. Two reconfiguration controllers are designed, the first is a generic controller that utilises standard concepts such as Direct Memory Access, burst mode transfer of data and interrupts to maximise throughput. This controller is then improved by the inclusion of a streaming decompression engine optimised for the Internal Configuration Access Port (ICAP) interface. This new controller significantly improves the reconfiguration speed of the system and throughputs of up to 385 Mbytes/sec are recorded. As power and energy become very important constraints in the system design, an investigation of the overheads associated with the use of the reconfiguration controller are experimentally quantified and presented.