Thinning Methodologies-A Comprehensive Survey
IEEE Transactions on Pattern Analysis and Machine Intelligence
Improving functional density using run-time circuit reconfiguration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fingerprint Image Enhancement: Algorithm and Performance Evaluation
IEEE Transactions on Pattern Analysis and Machine Intelligence
Computer Vision Algorithms on Reconfigurable Logic Arrays
IEEE Transactions on Parallel and Distributed Systems
Fingerprint Matching Using an Orientation-Based Minutia Descriptor
IEEE Transactions on Pattern Analysis and Machine Intelligence
Fingerprint enhancement with dyadic scale-space
Pattern Recognition Letters
Fingerprint verification using ridge direction distribution and minutiae correspondence
Systems and Computers in Japan
Validity of the single processor approach to achieving large scale computing capabilities
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration
DSD '08 Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
IDEA and AES, two cryptographic algorithms implemented using partial and dynamic reconfiguration
Microelectronics Journal
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
A new methodology to implement the AES algorithm using partial and dynamic reconfiguration
Integration, the VLSI Journal
An FPGA-Based Embedded System for Fingerprint Matching Using Phase-Only Correlation Algorithm
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Computer
Run-time self-reconfigurable 2D convolver for adaptive image processing
Microelectronics Journal
Dynamic Reconfiguration Optimisation with Streaming Data Decompression
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
A hardware solution for real-time intelligent fingerprint acquisition
Journal of Real-Time Image Processing
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This work aims to pave the way for an efficient open system architecture applied to embedded electronic applications to manage the processing of computationally complex algorithms at real-time and low-cost. The target is to define a standard architecture able to enhance the performance-cost trade-off delivered by other alternatives nowadays in the market like general-purpose multi-core processors. Our approach, sustained by hardware/software (HW/SW) co-design and run-time reconfigurable computing, is synthesizable in SRAM-based programmable logic. As proof-of-concept, a run-time partially reconfigurable field-programmable gate array (FPGA) is addressed to carry out a specific application of high-demanding computational power such as an automatic fingerprint authentication system (AFAS). Biometric personal recognition is a good example of compute-intensive algorithm composed of a series of image processing tasks executed in a sequential order. In our pioneer conception, these tasks are partitioned and synthesized first in a series of coprocessors that are then instantiated and executed multiplexed in time on a partially reconfigurable region of the FPGA. The implementation benchmark of the AFAS either as a pure software approach on a PC platform under a dual-core processor (Intel Core 2 Duo T5600 at 1.83 GHz) or as a reconfigurable FPGA co-design (identical algorithm partitioned in HW/SW tasks operating at 50 or 100 MHz on the second smallest device of the Xilinx Virtex-4 LX family) highlights a speed-up of one order of magnitude in favor of the FPGA alternative. These results let point out biometric recognition as a sensible killer application for run-time reconfigurable computing, mainly in terms of efficiently balancing computational power, functional flexibility and cost. Such features, reached through partial reconfiguration, are easily portable today to a broad range of embedded applications with identical system architecture.