An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fully pipelined memoryless 17.8 Gbps AES-128 encryptor
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Architectures and VLSI Implementations of the AES-Proposal Rijndael
IEEE Transactions on Computers
CT-RSA 2001 Proceedings of the 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA
AES Implementation on FPGA: Time - Flexibility Tradeoff
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
CARDIS '98 Proceedings of the The International Conference on Smart Card Research and Applications
A Novel Pipelined Threads Architecture for AES Encryption Algorithm
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Circuit Design with VHDL
A 2 Gb/s balanced AES crypto-chip implementation
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
High-speed VLSI architectures for the AES algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AES on FPGA from the fastest to the smallest
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
SoC: a real platform for IP reuse, IP infringement, and IP protection
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Journal of Signal Processing Systems
On the exploitation of a high-throughput SHA-256 FPGA design for HMAC
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
On the exploitation of a high-throughput SHA-256 FPGA design for HMAC
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Journal of Real-Time Image Processing
Exposing WPA2 security protocol vulnerabilities
International Journal of Information and Computer Security
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Wireless networks are very widespread nowadays, so secure and fast cryptographic algorithms are needed. The most widely used security technology in wireless computer networks is WPA2, which employs the AES algorithm, a powerful and robust cryptographic algorithm. In order not to degrade the Quality of Service (QoS) of these networks, the encryption speed is very important, for which reason we have implemented the AES algorithm in an FPGA, taking advantage of the hardware characteristics and the software-like flexibility of these devices. In this paper, we propose our own methodology for doing an FPGA-based AES implementation. This methodology combines the use of three hardware languages (Handel-C, VHDL and JBits) with partial and dynamic reconfiguration, and a pipelined and parallel implementation. The same design methodology could be extended to other cryptographic algorithms. Thanks to all these improvements our pipelined and parallel implementation reaches a very high throughput (24.922Gb/s) and the best efficiency (throughput/area ratio) of all the related works found in the literature (6.97Mb/s per slice).