A fully pipelined memoryless 17.8 Gbps AES-128 encryptor
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A 2 Gb/s balanced AES crypto-chip implementation
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Divide-and-concatenate: an architecture level optimization technique for universal hash functions
Proceedings of the 41st annual Design Automation Conference
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
A tamper resistant hardware accelerator for RSA cryptographic applications
Journal of Systems Architecture: the EUROMICRO Journal
An Instruction-Level Distributed Processor for Symmetric-Key Cryptography
IEEE Transactions on Parallel and Distributed Systems
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A High Performance Sub-Pipelined Architecture for AES
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A highly efficient AES cipher chip
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Reconfigurable system for high-speed and diversified AES using FPGA
Microprocessors & Microsystems
M-TREE: a high efficiency security architecture for protecting integrity and privacy of software
Journal of Parallel and Distributed Computing - Special issue: Security in grid and distributed systems
An area optimized reconfigurable encryptor for AES-Rijndael
Proceedings of the conference on Design, automation and test in Europe
Accelerated AES implementations via generalized instruction set extensions
Journal of Computer Security - The Third IEEE International Symposium on Security in Networks and Distributed Systems
Reconfigurable hardware for high-security/high-performance embedded systems: the SAFES perspective
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AES Encryption Implementation and Analysis on Commodity Graphics Processing Units
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Practical symmetric key cryptography on modern graphics hardware
SS'08 Proceedings of the 17th conference on Security symposium
An 8-bit systolic AES architecture for moderate data rate applications
Microprocessors & Microsystems
IDEA and AES, two cryptographic algorithms implemented using partial and dynamic reconfiguration
Microelectronics Journal
Parallel algorithms development for programmable devices with application from cryptography
International Journal of Parallel Programming
ISTASC'09 Proceedings of the 9th WSEAS International Conference on Systems Theory and Scientific Computation
DSPs, BRAMs, and a Pinch of Logic: Extended Recipes for AES on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A new methodology to implement the AES algorithm using partial and dynamic reconfiguration
Integration, the VLSI Journal
Enhancing the performance of symmetric-key cryptography via instruction set extensions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FastCrypto: parallel AES pipelines extension for general-purpose processors
Neural, Parallel & Scientific Computations
Configurable computing for high-security/high-performance ambient systems
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The technical analysis used in determining which of the potential Advanced Encryption Standard candidates was selected as the Advanced Encryption Algorithm includes efficiency testing of both hardware and software implementations of candidate algorithms. Reprogrammable devices such as field-programmable gate arrays (FPGAs) are highly attractive options for hardware implementations of encryption algorithms, as they provide cryptographic algorithm agility, physical security, and potentially much higher performance than software solutions. This contribution investigates the significance of FPGA implementations of the Advanced Encryption Standard candidate algorithms. Multiple architectural implementation options are explored for each algorithm. A strong focus is placed on high-throughput implementations, which are required to support security for current and future high bandwidth applications. Finally, the implementations of each algorithm will be compared in an effort to determine the most suitable candidate for hardware implementation within commercially available FPGAs.