An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Design of Rijndael
A fully pipelined memoryless 17.8 Gbps AES-128 encryptor
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
CT-RSA 2001 Proceedings of the 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA
Rijndael FPGA Implementations Utilising Look-Up Tables
Journal of VLSI Signal Processing Systems
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs
FCCM '08 Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines
Implementation of the AES-128 on virtex-5 FPGAs
AFRICACRYPT'08 Proceedings of the Cryptology in Africa 1st international conference on Progress in cryptology
Reconfigurable memory based AES co-processor
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
AES on FPGA from the fastest to the smallest
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
SP 800-38A 2001 edition. Recommendation for Block Cipher Modes of Operation: Methods and Techniques
SP 800-38A 2001 edition. Recommendation for Block Cipher Modes of Operation: Methods and Techniques
SP 800-38B. Recommendation for Block Cipher Modes of Operation: the CMAC Mode for Authentication
SP 800-38B. Recommendation for Block Cipher Modes of Operation: the CMAC Mode for Authentication
SP 800-38C. Recommendation for Block Cipher Modes of Operation: the CCM Mode for Authentication and Confidentiality
Securely sealing Multi-FPGA systems
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Configurable memory security in embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
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We present three lookup-table-based AES implementations that efficiently use the BlockRAM and DSP units embedded within Xilinx Virtex-5 FPGAs. An iterative module outputs a 32-bit AES round column every clock cycle, with a throughput of 1.67 Gbit/s when processing two 128-bit inputs. This construct is then replicated four times to provide a complete AES round per cycle with 6.7 Gbit/s throughput when processing eight input streams. This, in turn, is replicated ten times for a fully unrolled design providing over 52 Gbit/s of throughput. We also present implementations of a BRAM-based AES key-expansion, CMAC, and CTR modes of operation. Results for designs where DSPs are replaced by regular logic are also presented. The combination and arrangement of the specialized embedded functions available in the FPGA allows us to implement our designs using very few traditional user logic elements such as flip-flops and lookup tables, yet still achieve these high throughputs. HDL source code, simulation testbenches, and software tool commands to reproduce reported results for the three AES variants and CMAC mode are made publicly available. Our contribution concludes with a discussion on comparing cipher implementations in the literature, and why these comparisons can be meaningless without a common reporting methodology, or within the context of a constrained target application.