Applied cryptography (2nd ed.): protocols, algorithms, and source code in C
Applied cryptography (2nd ed.): protocols, algorithms, and source code in C
The Design of Rijndael
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
The MOLEN rho-mu-Coded Processor
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Two Methods of Rijndael Implementation in Reconfigurable Hardware
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
The MOLEN Polymorphic Processor
IEEE Transactions on Computers
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
IPSec Implementation on Xilinx Virtex-II Pro FPGA and Its Application
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Merged computation for Whirlpool hashing
Proceedings of the conference on Design, automation and test in Europe
Vectorized AES Core for High-throughput Secure Environments
High Performance Computing for Computational Science - VECPAR 2008
Cost-efficient SHA hardware accelerators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DSPs, BRAMs, and a Pinch of Logic: Extended Recipes for AES on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard
Computers and Electrical Engineering
| Hi-index | 0.00 |
We consider the AES encryption/decryption algorithm and propose a memory based hardware design to support it. The proposed implementation is mapped on the Xilinx Virtex II Pro technology. Both the byte substitution and the polynomial multiplication of the AES algorithm are implemented in a single dual port on-chip memory block (BRAM). Two AES encryption/ decryption cores have been designed and implemented on a prototyping XC2VP20-7 FPGA: a completely unrolled loop structure capable of achieving a throughput above 34 Gbits/s, with an implementation cost of 3513 slices and 80 BRAMs; and a fully folded structure, requiring only 515 slices and 12 BRAMs, capable of a throughput above 2 Gbits/s. To evaluate the proposed AES design, its has been embedded in a polymorphic processor organization, as a reconfigurable co-processor. Comparisons to state-of-the-art AES cores indicate that the proposed unfolded core outperforms the most recent works by 34% in throughput and requires 68% less reconfigurable area. Experimental results of both folded and unfolded AES cores suggest over 560% improvement in the throughput/slice metric when compared to the recent AES related art.