The Design of Rijndael
The MOLEN Polymorphic Processor
IEEE Transactions on Computers
A compact FPGA implementation of the hash function whirlpool
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Reconfigurable memory based AES co-processor
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Improving SHA-2 hardware implementations
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Finding collisions in the full SHA-1
CRYPTO'05 Proceedings of the 25th annual international conference on Advances in Cryptology
Efficient architecture and hardware implementation of the Whirlpool hash function
IEEE Transactions on Consumer Electronics
Isolated WDDL: A Hiding Countermeasure for Differential Power Analysis on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Hardware evaluation of the stream cipher-based hash functions RadioGatún and irRUPT
Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents an improved hardware structure for the computation of the Whirlpool hash function. By merging the round key computation with the data compression and by using embedded memories to perform part of the Galois Field (28) multiplication, a core can be implemented in just 43% of the area of the best current related art while achieving a 12% higher throughput. The proposed core improves the Throughput per Slice compared to the state of the art by 160%, achieving a throughput of 5.47 Gbit/s with 2110 slices and 32 BRAMs on a VIRTEX II Pro FPGA. Results for a real application are also presented by considering a polymorphic computational approach.