An FPGA Based SHA-256 Processor
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
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ISC '02 Proceedings of the 5th International Conference on Information Security
The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512)
Proceedings of the conference on Design, automation and test in Europe - Volume 3
An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)
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Implementation of the SHA-2 Hash Family Standard Using FPGAs
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PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Proceedings of the conference on Design, automation and test in Europe
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CANS '08 Proceedings of the 7th International Conference on Cryptology and Network Security
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Information Security and Cryptology
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WISA'07 Proceedings of the 8th international conference on Information security applications
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CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
On the exploitation of a high-throughput SHA-256 FPGA design for HMAC
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
On the exploitation of a high-throughput SHA-256 FPGA design for HMAC
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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ICICS'12 Proceedings of the 14th international conference on Information and Communications Security
FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256
Microprocessors & Microsystems
Compact and unified hardware architecture for SHA-1 and SHA-256 of trusted mobile computing
Personal and Ubiquitous Computing
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This paper proposes a set of new techniques to improve the implementation of the SHA-2 hashing algorithm. These techniques consist mostly in operation rescheduling and hardware reutilization, allowing a significant reduction of the critical path while the required area also decreases. Both SHA256 and SHA512 hash functions have been implemented and tested in the VIRTEX II Pro prototyping technology. Experimental results suggest improvements to related SHA256 art above 50% when compared with commercial cores and 100% to academia art, and above 70% for the SHA512 hash function. The resulting cores are capable of achieving the same throughput as the fastest unrolled architectures with 25% less area occupation than the smallest proposed architectures. The proposed cores achieve a throughput of 1.4 Gbit/s and 1.8 Gbit/s with a slice requirement of 755 and 1667 for SHA256 and SHA512 respectively, on a XC2VP30-7 FPGA.