Cost-efficient SHA hardware accelerators

Authors:
Ricardo Chaves;Georgi Kuzmanov;Leonel Sousa;Stamatis Vassiliadis
Affiliations:
Instituto Superior Técnico/INESC-ID, Lisbon, Portugal, and Computer Engineering Department, EEMCS, Delft University of Technology, Delft, The Netherlands;Computer Engineering Department, EEMCS, Delft University of Technology, Delft, The Netherlands;Instituto Superior Técnico/INESC-ID, Lisbon, Portugal;Computer Engineering, EEMCS, Delft University of Technology, Delft, The Netherlands
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2008

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Abstract

This paper presents a new set of techniques for hard-ware implementations of Secure Hash Algorithm (SHA) hash functions. These techniques consist mostly in operation rescheduling and hardware reutilization, therefore, significantly decreasing the critical path and required area. Throughputs from 1.3 Gbit/s to 1.8 Gbit/s were obtained for the SHA implementations on a Xilinx VIRTEX II Pro. Compared to commercial cores and previously published research, these figures correspond to an improvement in throughput/slice in the range of 29% to 59% for SHA-1 and 54% to 100% for SHA-2. Experimental results on hybrid hardware/software implementations of the SHA cores, have shown speedups up to 150 times for the proposed cores, compared to pure software implementations.